Array Substrate Gate Line Layout for Lower TFT Coupling Delay
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Solution Overview
Problem
In large-sized liquid crystal displays, the coupling capacitances between gate and data lines cause signal delays due to longer charging times, which are exacerbated by the presence of coupling capacitances between the gate and source/drain of thin film transistors.
Innovation Solution
The array substrate incorporates a widening portion with a recess structure in the gate lines between adjacent data lines, reducing the resistance and charging time of coupling capacitances, while the recess structure overlaps with the drain of the thin film transistor to minimize overlapping and coupling capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the gate line width is increased to reduce resistance and charging time, then the signal delay is reduced, but the coupling capacitance at intersections with data lines increases
Solution Approach 1:
The gate line is designed with varying width along its length: wider sections are positioned between data lines to reduce resistance and charging time, while narrower sections are positioned at intersections with data lines to minimize coupling capacitance. This local variation in geometric properties allows the gate line to optimize both electrical parameters at different locations.
Solution Approach 2:
The gate line structure is extended into the vertical dimension by adding a recess portion that protrudes downward from the gate line plane. This three-dimensional structure reduces the horizontal width of the gate line at intersections, thereby reducing coupling capacitance with data lines while maintaining sufficient conductive cross-section to keep resistance low.
2Ease of manufacture
If the gate line width is maintained uniformly, then the manufacturing process is simple, but the signal delay increases due to higher resistance
Solution Approach 1:
The gate line incorporates localized structural variations (widening portions and recess portions) at specific locations rather than maintaining uniform dimensions throughout. These localized modifications are integrated into the existing manufacturing process, adding minimal complexity while significantly improving electrical performance by reducing resistance in critical sections.
3Productivity
If the gate line width is increased to reduce resistance, then the charging time decreases, but the area occupied by the gate line increases
Solution Approach 1:
The gate line utilizes the vertical dimension by incorporating recess portions that extend downward from the gate line plane. This allows the gate line to achieve lower resistance (equivalent to wider horizontal dimensions) without proportionally increasing the planar footprint, as the additional conductive material is arranged in the vertical direction rather than expanding the horizontal area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces signal delay in the gate lines by decreasing the time required to charge coupling capacitances and minimizing coupling capacitances between the gate and data lines, while allowing for flexible wiring and maintaining a balanced voltage application.
Implementation Method 1
decreases the time needed to charge coupling capacitances and reduces signal delay in gate lines
Implementation Method 2
coupling capacitances between gate and source/drain of thin film transistors
Data Source
AI summary
An array substrate and a display device are disclosed. The array substrate includes a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a pixel electrode arranged in a region defined by an adjacent gate line and an adjacent data line, and a thin film transistor arranged at an intersection of the gate lines and the data lines. A drain of the thin film transistor is connected with the pixel electrode through a via hole. The gate lines further include a widening portion between adjacent data lines. The widening portion comprises a recess structure. An orthogonal projection of the recess structure on the base substrate at least partly overlaps that of the drain of the thin film transistor on the base substrate.