Tiered 3D NAND Stack for Stable Replacement Gate Formation
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Solution Overview
Problem
Conventional 3D NAND memory devices face challenges in accurately forming conductive structures due to deformation of insulative structures during the replacement gate process, which can close off voids and inhibit the formation of conductive structures, especially in regions with long unsupported sections.
Innovation Solution
A method involving a precursor stack with insulative structures vertically alternating with both partially-sacrificial structures, where the first and second partially-sacrificial structures are selectively removed in stages to form voids for conductive structure formation, maintaining structural integrity and reliability by ensuring multiple structures remain above each void, reducing deformation risk and expanding processing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sacrificial structures are removed to form voids for conductive structures, then conductive structure formation is enabled, but insulative structures deform into voids closing them off
Solution Approach 1:
The patent segments the removal process into multiple stages, removing sacrificial structures in sequential batches rather than all at once. This is achieved through multiple etch cycles with different etch selectivities, where each cycle removes a portion of sacrificial structures while leaving others intact to provide support. The segmentation prevents insulative structures from deforming into voids by maintaining structural support during the formation process.
Solution Approach 2:
The patent performs preliminary actions by forming a complete stack with all sacrificial structures in place before removing any. The insulative structures are first formed with full sacrificial structure support, establishing their final positions and configurations. Only after this preliminary formation is complete does the selective removal process begin, ensuring insulative structures are already stabilized before voids are created.
2Device complexity
If insulative structures have long unsupported sections, then device complexity is reduced, but deformation risk increases
Solution Approach 1:
The patent introduces dynamics into the fabrication process by making the structural support configuration change over time. Different sacrificial structures are removed at different stages, dynamically adjusting the support configuration. This allows insulative structures to have longer spans in the final device while maintaining support during critical formation stages, effectively decoupling final device complexity from manufacturing precision requirements.
3Productivity
If multiple sacrificial structures are removed simultaneously, then processing time is reduced, but insulative structure deformation increases
Solution Approach 1:
The patent applies periodic action through multiple etch cycles, each removing a specific portion of sacrificial structures. Rather than a single continuous removal process, the fabrication uses periodic etch steps separated by stabilization periods where insulative structures can settle. This periodic approach balances productivity by automating multiple cycles while maintaining precision through controlled间歇性 removal.
Data Source
AI summary
Microelectronic devices include a region with a tiered stack that includes insulative, conductive, and non-conductive structures arranged in tiers. The insulative structures vertically alternate with both the conductive and the non-conductive structures. Each of the conductive structures is vertically spaced from another of the conductive structures by at least one of the non-conductive structures and at least two of the insulative structures. A composition of the non-conductive structures differs from a composition of the insulative structures. In methods of fabrication, a precursor stack is formed to include the insulative structures vertically alternating with first and second non-conductive structures. In a region of the precursor stack, the first non-conductive structures are removed, forming voids between multi-structure tier groups. Conductive structures are formed in the voids. Electronic systems are also disclosed.