Back-Illuminated SOI Sensor With Boron Layer for Deep UV Detection
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Solution Overview
Problem
Current image sensors face challenges in efficiently detecting high-energy photons at deep UV and vacuum UV wavelengths due to high reflectivity and absorption issues, leading to low signal-to-noise ratios and potential damage from high-intensity light sources, especially when operating at high temperatures that can damage CMOS circuits.
Innovation Solution
The development of a back-thinned image sensor with a boron layer and a monotonically decreasing p-type dopant concentration gradient on a silicon on insulator wafer, allowing for finer metal interconnects and higher sensitivity, while maintaining a flat wafer surface for efficient photon detection and reducing the risk of thermal damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a back-thinned sensor structure is used to improve quantum efficiency, then photon detection sensitivity is improved, but the sensor becomes more vulnerable to thermal damage and contamination
Solution Approach 1:
A boron layer is introduced as an intermediary between the silicon substrate and the external environment. This boron layer serves as a protective mediator that prevents thermal damage and contamination to the back-thinned sensor surface while maintaining high photon detection efficiency through its optical transparency and thermal protective properties.
Solution Approach 2:
The boron layer is deposited beforehand to create a protective cushion on the back surface of the thinned sensor. This pre-established protective layer cushions the sensor against thermal shocks and contamination before exposure to harsh environments, preventing direct damage to the sensitive photodetector elements.
2Measurement precision
If high-intensity light sources are used to improve signal-to-noise ratio, then detection capability is improved, but thermal damage to CMOS circuits increases
Solution Approach 1:
The sensor structure is segmented into distinct functional layers: a front side for CMOS circuit integration and a back side for photon detection. This segmentation allows the back-thinned detection region to receive high-intensity light for improved signal-to-noise ratio while the front side CMOS circuits are protected from direct thermal exposure through the silicon substrate barrier.
3Manufacturing precision
If finer metal interconnects are implemented to improve resolution, then inspection capability is improved, but manufacturing complexity increases
Solution Approach 1:
The sensor utilizes back-side illumination to detect photons, effectively moving the detection function to another dimension (the back surface) away from the front-side CMOS circuits and metal interconnects. This dimensional separation allows finer metal interconnects to be implemented on the front side for improved inspection resolution without the interconnects being in the direct path of high-intensity inspection light, thereby reducing manufacturing complexity related to light-induced damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quantum efficiency and longevity of image sensors under high radiation flux, enabling finer design rules and more efficient charge-to-voltage conversion, while preventing thermal damage to CMOS circuits and improving interconnect capabilities.
Implementation Method 1
back-thinned image sensor with a boron layer and a monotonically decreasing p-type dopant concentration gradient on a silicon on insulator wafer, allowing for finer metal interconnects and higher sensitivity
Implementation Method 2
silicon on insulator wafer, allowing for finer metal interconnects and higher sensitivity
Data Source
AI summary
An image sensor is fabricated by first heavily p-type doping the thin top monocrystalline silicon substrate of an SOI wafer, then forming a relatively lightly p-doped epitaxial layer on a top surface of the top silicon substrate, where p-type doping levels during these two processes are controlled to produce a p-type dopant concentration gradient in the top silicon substrate. Sensing (circuit) elements and associated metal interconnects are fabricated on the epitaxial layer, then the handling substrate and oxide layer of the SOI wafer are at least partially removed to expose a lower surface of either the top silicon substrate or the epitaxial layer, and then a pure boron layer is formed on the exposed lower surface. The p-type dopant concentration gradient monotonically decreases from a maximum level near the top-silicon/epitaxial-layer interface to a minimum concentration level at the epitaxial layer's upper surface.


