FinFET Select Transistor for Resistive Memory Cell Scaling
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Solution Overview
Problem
Conventional memory technologies, such as flash memory and DRAM, face scaling limits and challenges due to high switching voltages and limited read/write cycles, prompting the need for alternative memory technologies that do not rely on electrical charge storage, such as resistivity changing memory technologies like MRAM and PCRAM, which require high write currents, making it difficult to achieve small cell sizes and high densities.
Innovation Solution
The use of FinFET transistors, which have an effective channel length dependent on the height of a 'fin' surrounded by a dielectric gate oxide layer, allows for high current drive while achieving cell sizes below 10F^2, enabling competitive memory device densities with reduced transistor width and improved cell layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional memory technologies (flash memory, DRAM) are used, then electrical charge storage is achieved, but scaling limits and high switching voltages prevent further miniaturization
Solution Approach 1:
The patent changes the fundamental operating parameter from electrical charge storage to resistivity change. By using materials that exhibit resistivity changes (such as phase-change materials or magnetoresistive materials), the memory cell can be miniaturized without being constrained by the scaling limits of charge-based memory, thereby resolving the contradiction between cell size reduction and reliability
Solution Approach 2:
The patent replaces the electrical charge storage mechanism with a resistivity change mechanism. Instead of relying on trapped electrical charges that require high switching voltages, the invention uses materials whose resistance changes state, enabling lower voltage operation and further miniaturization while maintaining reliability
2Adaptability or versatility
If resistivity changing memory technologies (MRAM, PCRAM) are used, then alternative storage mechanism is achieved, but high write currents are required which increase cell size
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional FinFET structures. The FinFET's vertical fin allows the channel to be accessed from multiple sides (top, bottom, and sidewalls), effectively increasing the channel width without increasing the lateral footprint. This enables the memory cell to drive the required write currents while maintaining a small cell area, resolving the contradiction between adaptability and cell area
Solution Approach 2:
The FinFET structure nests the channel within the fin, with the gate wrapping around three sides of the fin structure. This nested configuration maximizes the gate-controlled channel area within a minimal lateral footprint, enabling high current drive capability in a compact cell area
3Power
If FinFET is used, then high current drive is achieved with reduced transistor width, but manufacturing complexity increases
Solution Approach 1:
The FinFET introduces a vertical dimension to the transistor channel, allowing current to flow through a three-dimensional fin structure rather than a planar channel. This vertical channel provides enhanced current drive capability while the gate controls the channel from multiple sides, achieving high power without proportionally increasing lateral device footprint or manufacturing complexity
Data Source
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AI summary
An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element (802). The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET (808) including a source (806), a drain (810), and a fin structure (872) formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer (816) formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.