Oxide TFT Array Substrate Layout With Five-Mask Self-Alignment
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Solution Overview
Problem
The high cost of manufacturing oxide semiconductor array substrates is attributed to the requirement of multiple masks in the manufacturing process, which increases production costs.
Innovation Solution
A reduced-mask process for manufacturing array substrates, involving five patterning processes, where a substrate with source and drain electrodes, an active layer, and a gate electrode is created using insulating layers and connecting electrodes, with specific contact holes and overlapping configurations to minimize the number of masks needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional multi-mask process is used for manufacturing oxide semiconductor array substrates, then manufacturing precision and reliability are improved, but manufacturing cost increases due to higher quantity of masks required
Solution Approach 1:
The patent merges multiple patterning steps into fewer steps by using the gate electrode pattern as a self-aligned mask for forming the active layer pattern, and subsequently as a mask for forming the insulating layer pattern. This consolidation reduces the total number of masks from 7-8 to just 3 masks (first, second, and third masks for different stages), thereby lowering manufacturing cost while maintaining precision through self-alignment.
Solution Approach 2:
The gate electrode pattern serves multiple functions: it acts as the functional gate electrode, serves as a self-aligned mask for active layer formation, and serves as a mask for insulating layer patterning. This multi-functionality eliminates the need for separate masks for these alignment-critical steps, reducing mask quantity and cost while ensuring precise alignment.
2Ease of manufacture
If number of masks is reduced to lower manufacturing cost, then manufacturing precision and alignment accuracy may deteriorate
Solution Approach 1:
The gate electrode pattern serves as its own alignment reference and mask for subsequent patterning steps. By using the already-formed gate electrode as the mask for active layer and insulating layer formation, the process achieves self-alignment, eliminating the need for additional alignment marks and ensuring high precision without requiring extra masks.
Solution Approach 2:
The gate electrode is formed first with precise patterning using the second mask, establishing a precise reference pattern before subsequent steps. This preliminary formation of the gate electrode pattern creates the alignment foundation for all subsequent self-aligned patterning steps, ensuring that reduced mask count does not compromise precision.
Data Source
AI summary
An array substrate is manufactured by five time patterning processes and includes connecting electrodes. The connecting electrodes include a first connecting electrode and a second connecting electrode. The first connecting electrode is in contact with the source electrode contact area through the first contact hole and in contact with the source electrode through the third contact hole. The second connecting electrode is in contact with the drain electrode contact area through the second contact hole, and in contact with the drain electrode through the fourth contact hole.