Multilayer Gate Layer Etching to Prevent Display Short Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of protrusion portions on the side surfaces of gate layers during the etching process in display device manufacturing can lead to short circuits with other conductive layers, deteriorating voltage characteristics in capacitors.
Innovation Solution
A display device design with a gate layer having side surfaces without protrusions, achieved by using a multilayer structure where the first metal (e.g., titanium) has a lower etch rate than the second metal (e.g., aluminum), resulting in acute angles that prevent the formation of protrusions, and through holes and grooves that allow for direct contact between conductive layers without external protrusions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an etching process is applied to the gate layer, then the gate layer can be formed, but protrusion portions are formed on the side surface of the gate layer
Solution Approach 1:
The gate layer is formed as a composite structure with a first gate layer including a first metal and a second gate layer including a second metal. The different metals have different etch rates, allowing the slower-etching first metal to prevent protrusion formation while the faster-etching second metal is removed more completely by the etching process.
Solution Approach 2:
The invention changes the material composition parameter of the gate layer from a single metal to a multi-layer structure with different etch rates. This parameter change allows the etching process to selectively remove material at different rates, preventing protrusion formation on the side surface.
2Ease of manufacture
If protrusion portions are formed on the gate layer side surface, then the gate layer structure is created, but short circuits occur with other conductive layers
Solution Approach 1:
The composite gate layer structure with different metal layers provides differential etching behavior that prevents protrusion formation. The slower-etching first metal acts as a barrier that maintains side surface flatness, preventing electrical contact with adjacent conductive layers and ensuring reliable insulation.
Solution Approach 2:
The first gate layer with lower etch rate is deposited beforehand to prevent the formation of protrusions that would cause short circuits. This preliminary layer counteracts the harmful effect of protrusion formation by maintaining a flat side surface profile during the etching process.
3Productivity
If the gate layer has protrusion portions, then the etching process is effective, but voltage characteristics of capacitors deteriorate
Solution Approach 1:
The multi-layer gate structure enables selective etching where the second metal is removed efficiently while the first metal remains to maintain side surface flatness. This composite structure allows effective etching productivity while preventing protrusion-induced short circuits that would deteriorate capacitor voltage characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the roughness of the gate layer's side surfaces and minimizes the risk of short circuits, thereby maintaining the voltage characteristics of capacitors and improving manufacturing efficiency.
Implementation Method 1
an etch rate of the first metal may be lower than an etch rate of the second metal under a same condition
Data Source
AI summary
A display device includes a substrate, a semiconductor layer disposed on the substrate, a gate insulating layer disposed on the semiconductor layer, a gate layer including a first layer disposed on the gate insulating layer and including a first metal, and a second layer disposed on the first layer and including a second metal, where a first through hole is defined through the second layer in a direction perpendicular to an upper surface of the first layer, and an interlayer insulating layer disposed on the gate layer.