Monolithic Micro LED Array Structure to Reduce Surface Recombination
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Solution Overview
Problem
Micro LED arrays face challenges in achieving high integration density, smaller LEDs, and smaller pitch while minimizing non-radiative recombination, particularly surface recombination, during the manufacturing process.
Innovation Solution
A method for forming monolithic LED array precursors involves growing specific structures with electronically isolated LED structures, providing electrical contact only on a specific area, and using selective area growth techniques to reduce surface recombination and enhance light emission properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form perimeters of active regions, then electrical isolation of individual micro LEDs is achieved, but surface recombination increases leading to reduced light emission efficiency
Solution Approach 1:
The patent extracts the harmful etching step from the manufacturing process by replacing it with selective area growth. The mask layer is selectively removed to expose specific regions for growth, eliminating the need for perimeter etching that causes surface damage and non-radiative recombination.
Solution Approach 2:
Instead of using etching to define active region perimeters (subtractive approach), the patent uses selective area growth (additive approach) to form the active regions. This inverts the conventional process sequence, growing material only in desired areas rather than removing material to create boundaries.
2Adaptability or versatility
If pick and place technique is used to assemble individual micro LEDs, then LEDs with different properties can be transferred onto the product substrate, but pick and place accuracy and transfer time deteriorate with high integration density requirements
Solution Approach 1:
The patent merges multiple individual LED fabrication processes into a single monolithic growth process. All micro LEDs are grown simultaneously on a common substrate using selective area growth, eliminating the need for separate fabrication and assembly steps for each LED.
Solution Approach 2:
The patent performs preliminary monolithic growth of all LED structures on a substrate before final transfer. The complete array of micro LEDs with their electrical isolation and active regions is formed in advance through a single growth process, preparing the entire structure for subsequent bulk transfer.
3Productivity
If monolithic integration is used to fabricate micro LED arrays, then higher integration density and smaller pitch are achieved, but colorization techniques become more complex for full color displays
Solution Approach 1:
The patent applies local quality by varying the composition and properties of semiconductor layers in different regions of the monolithic structure. Different active region compositions can be grown in different areas to emit different wavelengths, enabling color differentiation without complex post-growth modifications.
4Loss of energy
If selective area growth is used to achieve electrically isolated active regions, then etching steps are eliminated reducing surface recombination, but mask patterning complexity increases
Solution Approach 1:
The patent uses a continuous mask layer that covers the entire substrate surface, then selectively removes portions to expose growth areas. This partial removal approach is simpler than creating precise perimeter patterns, as the mask defines positive spaces rather than requiring precise negative space definition around each LED.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in improved light emission properties and reduced non-radiative recombination, leading to increased internal and external quantum efficiencies, and enables the production of micro LED arrays with higher integration density and smaller dimensions.
Implementation Method 1
forming a continuous first semiconductor layer on the surface of the substrate; growing a second semiconductor layer on unmasked portions of the first semiconductor layer
Implementation Method 2
Light emitting diode (LED) arrays; group III-nitride-based micro LEDs are inorganic semiconductor LEDs
Data Source
Figure 1A~1B
Figure 2~3
Figure 4A~4C
AI summary
A monolithic LED array precursor comprising a plurality of LED structures sharing a first semiconductor layer, wherein the first semiconductor layer defines a plane of the LED array precursor, each LED structure comprising (i) a second semiconductor layer on the first semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the second semiconductor layer has sloped sides, (ii) a third semiconductor layer on the second semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the third semiconductor layer has sloped sides parallel to the sloped sides of the second semiconductor layer, (iii) a fourth semiconductor layer on the third semiconductor layer, having an upper surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross-section normal to the upper surface portion, such that the fourth semiconductor layer has sloped sides parallel to the sloped sides of the third semiconductor layer, (iv) a primary electrical contact on the fourth semiconductor layer, wherein the contact is only on the upper surface portion of the fourth semiconductor layer which is parallel to the plane of the LED array precursor, (v) electrically insulating, optically transparent spacers on the sloped sides of the fourth semiconductor layer, the spacers having an internal surface facing the sloped sides of the fourth semiconductor layer and an opposing external surface and (vi) a reflecting layer, electrically conducting extending over the external surface of the spacers, wherein the third semiconductor layer comprises a plurality of quantum well sub-layers, the quantum well sub-layers having a greater thickness on a portion parallel to the plane of the LED array precursor and a reduced thickness on a portion which is not parallel to the plane of the LED array precursor.