3D Gate Structure Isolation for High-Density Semiconductor Memory
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Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by each memory cell, making further improvements in two-dimensional designs challenging, prompting the development of three-dimensional semiconductor devices to enhance integration and reliability.
Innovation Solution
A three-dimensional semiconductor device structure featuring a gate structure with multiple conductive layers and an isolation structure, where the third conductive layer acts as an etch stop and is thicker than the first and second layers, and a manufacturing method involving trench formation and insulating spacer use to create stable channel structures and isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor devices are developed to improve integration, then the degree of integration is enhanced, but the structural complexity and manufacturing difficulty increase
Solution Approach 1:
The gate structure is segmented into multiple conductive layers (first, second, and third conductive layers) with different thicknesses and functions. The isolation structure is segmented into a first portion and a second portion that protrudes into the third conductive layer. This segmentation allows complex 3D functionality to be achieved through modular layering rather than monolithic complex structures.
Solution Approach 2:
The patent transitions from two-dimensional planar structures to three-dimensional stacked structures by adding vertical layering. Multiple conductive layers are stacked in the vertical dimension, and the isolation structure extends vertically with its second portion protruding into upper layers. This dimensional transition enables higher integration density without proportionally increasing manufacturing complexity.
2Manufacturing precision
If the third conductive layer is made thicker to serve as an etch stop, then etching precision is improved, but the area occupied by the gate structure increases
Solution Approach 1:
The third conductive layer is designed with greater thickness than the first and second conductive layers in advance, serving as a pre-established etch stop layer. This preliminary design feature ensures that subsequent etching processes can reliably stop at the third conductive layer, improving etching precision without requiring additional etch stop layers or complex process controls.
3Reliability
If the isolation structure extends into channel structures, then operational reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The isolation structure exhibits local quality differentiation: the first portion passes through the second conductive layer and extends into channel structures to provide electrical isolation and improve reliability, while the second portion protrudes from the first portion into the third conductive layer to serve as an etch stop. Each portion has optimized properties for its specific function, allowing the structure to meet reliability requirements without uniformly increasing manufacturing precision across the entire isolation structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the degree of integration and operational reliability of semiconductor devices by minimizing voids and preventing damage to peripheral layers, while allowing for improved processing characteristics and manufacturing efficiency.
Implementation Method 1
forming an insulating spacer for exposing the third conductive layer in the trench; etching the third conductive layer by using the insulating spacer as an etch barrier
Implementation Method 2
forming a trench passing through the second conductive layer and exposing the third conductive layer; forming a first trench by etching the stack and the channel structures
Data Source
AI summary
A semiconductor device may include a gate structure including a first conductive layer, a second conductive layer, and a third conductive layer, the third conductive layer being disposed between the first conductive layer and the second conductive layer and thicker than the first conductive layer and the second conductive layer, channel structures passing through the gate structure, and an isolation structure including a first portion passing through the second conductive layer and extended into the channel structures and a second portion protruding from the first portion into the third conductive layer and disposed between the channel structures.