Dual-Channel Gate Capacitance Structure for Linear RF Power Amplifiers

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Solution Overview

Problem

Spectral regrowth in transmitter circuits due to nonlinearity in power amplifiers leads to interference and bit errors, primarily caused by amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions, which existing technologies have not adequately addressed.

Innovation Solution

The implementation of semiconductor devices with a gate capacitance that is electrostatically coupled to both negatively and positively charged carrier channels, providing a linear and constant capacitance profile to reduce these distortions, utilizing a combination of gallium nitride and aluminum gallium nitride layers to achieve improved linearity in RF power amplifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional FET with single-polarity carrier channel is used, then the device structure is simple, but the gate capacitance is non-linear causing AM-AM and AM-PM distortions

Engineering Contradiction:
Improvesignal qualityVSAvoiddevice structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines a first FET with negatively charged carrier channel and a second FET with positively charged carrier channel into a single integrated device structure. Both FETs share a common gate terminal that electrostatically controls both carrier channels, creating a unified device that produces linear capacitance response while maintaining controlled complexity through shared components

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If power amplifier operates in linear region to reduce spectral regrowth, then signal quality improves, but power efficiency decreases

Engineering Contradiction:
Improvesignal qualityVSAvoidpower efficiency
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the fundamental parameter of gate capacitance from non-linear to linear by introducing dual-polarity carrier channels. This parameter change allows the power amplifier to maintain improved signal quality with reduced spectral regrowth while operating at higher efficiency points, as the linear capacitance reduces the distortion mechanisms that previously forced operation into linear region

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If non-linearity in gate capacitance is present, then device complexity is low, but spectral regrowth and interference increase

Engineering Contradiction:
Improvegate capacitance structureVSAvoidspectral regrowth
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the typically harmful non-linear capacitance effect into a beneficial linear response by using dual-polarity carrier channels. The complementary nature of positive and negative charge channels causes their non-linear capacitance effects to cancel each other out, transforming what would be a source of distortion into a source of linearity and reduced spectral regrowth

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces signal distortion and interference by maintaining a flat capacitance response across a range of gate voltages, thereby minimizing AM-AM and AM-PM distortions, leading to improved signal quality in RF transmission.

Implementation Method 1

a gate terminal electrostatically coupled to both the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component

Methodology Applied
Scientific EffectElectrostatic coupling: Electrostatics

Data Source

PatentUS12113061B2Semiconductor device with linear capacitance
Publication Date: 2024.10.08 MASSACHUSETTS INST OF TECH
  • US12113061B2 patent drawing
  • US12113061B2 patent drawing
  • US12113061B2 patent drawing

AI summary

A semiconductor device having relatively linear and constant parasitic capacitance of an operation range includes a first component having a negatively charged carrier channel and a second component comprising a positively charged carrier channel. The first component has source terminal and a drain terminal. The second component has bias terminal. Both components share a gate terminal that is electrostatically coupled to the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component to produce a capacitance profile that stays relatively linear and constant as a voltage at the gate terminal changes.