Aligned-Finger ESD Protection Circuit for Reduced Chip Area

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Solution Overview

Problem

Existing ESD protection solutions for integrated circuits result in oversizing of protection circuits, leading to increased semiconductor surface area and inefficiencies, particularly when individually sizing circuits for each pin.

Innovation Solution

An ESD protection device comprising a semiconductor electronic switch and a diode, both with aligned fingers, configured in parallel to efficiently withstand electrostatic discharge voltages, allowing for modular design and reduced surface area occupation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ESD protection circuits are individually sized according to wiring provided with package pins, then ESD protection level for each input/output is optimized, but design time increases significantly

Engineering Contradiction:
ImproveESD protection levelVSAvoiddesign time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The ESD protection circuit is segmented into modular units (first ESD protection circuit, second ESD protection circuit, etc.) that can be independently designed and then replicated. Each module corresponds to a group of pins with similar wiring characteristics, allowing standardized design while maintaining optimization for different pin configurations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates universal ESD protection modules that can serve multiple functions - each module type can protect multiple pins with similar characteristics. The first ESD protection circuit protects first group of pins, the second ESD protection circuit protects second group of pins, and so on, with each circuit type being reusable across multiple pins.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If ESD protection circuits are oversized to guarantee sufficient protection level for package pins, then ESD protection level for package pins is sufficient, but semiconductor occupied surface area increases significantly

Engineering Contradiction:
ImproveESD protection levelVSAvoidsemiconductor occupied surface area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Different ESD protection circuits are assigned to different groups of pins based on their specific wiring characteristics and protection requirements. The first ESD protection circuit is optimized for the first group of pins, the second for the second group, etc., allowing each circuit to be precisely sized for its specific function rather than all circuits being oversized to handle the maximum requirement.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The total ESD protection requirement is segmented into multiple smaller protection circuits, each handling a specific group of pins. This segmentation allows the total surface area to be distributed efficiently across multiple specialized circuits rather than requiring one large oversized circuit.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250081627A1ESD protection device of an integrated circuit
Publication Date: 2025.03.06 STMICROELECTRONICS INT NV
  • US20250081627A1 patent drawing
  • US20250081627A1 patent drawing

AI summary

An ESD protection device includes at least one semiconductor electronic switch electrically coupled in parallel with a diode. The semiconductor electronic switch and the diode each include at least one finger extending substantially parallel to a first direction. The fingers of the semiconductor electronic switch and of the diode are aligned with each other along this first direction.