Smart Erase Scheme for Non-Volatile Memory
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Solution Overview
Problem
Conventional erase operations in non-volatile memory devices often require multiple loops to complete, which can increase time and become challenging, especially at the end of a device's life, due to limited control over erase depth and quantized voltage steps.
Innovation Solution
A smart erase scheme that applies a first erase voltage pulse, determines the upper tail of the threshold voltage distribution, and adjusts a second erase pulse based on this distribution, slope, and verify level to ensure efficient completion within two loops, allowing for additional loops if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional erase operations use multiple loops with fixed voltage steps, then the erase operation can be completed, but the time required increases and control over erase depth becomes limited
Solution Approach 1:
The patent applies dynamic adjustment of erase voltage pulses based on real-time threshold voltage distribution feedback. Instead of using fixed quantized voltage steps, the system dynamically determines the upper tail of the threshold voltage distribution and adjusts subsequent erase pulses accordingly, enabling precise control over erase depth while reducing the number of loops required
Solution Approach 2:
The patent implements a feedback mechanism where the upper tail of the threshold voltage distribution is determined after each erase pulse, and this information is used to determine the magnitude of subsequent erase pulses. This closed-loop feedback enables precise control of erase depth and allows the operation to complete in fewer loops compared to conventional open-loop approaches
2Ease of manufacture
If conventional erase operations use quantized voltage steps, then the implementation is simplified, but the control over erase depth becomes limited and challenging especially at end of device life
Solution Approach 1:
The patent changes the parameter control approach from fixed quantized voltage steps to continuous adjustment based on threshold voltage distribution characteristics. By determining the upper tail of the distribution and using it to calculate subsequent erase pulse magnitudes, the system achieves both ease of implementation through standardized procedures and high reliability through adaptive parameter adjustment
Solution Approach 2:
The patent performs preliminary determination of the upper tail of the threshold voltage distribution before applying subsequent erase pulses. This preliminary action provides critical information about the current erase state, enabling more reliable control over the erase depth and ensuring consistent performance even at end of device life
Data Source
AI summary
A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.