Array Substrate Common Electrode Shielding for Scan Wire Crosstalk

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Solution Overview

Problem

In ultra-high definition liquid crystal displays with narrow bezels, parasitic capacitors formed between vertical scan wires and pixel electrodes cause crosstalk, affecting display quality.

Innovation Solution

The array substrate design includes a scan wiring layer with a vertical scan wire and a common electrode layer where the horizontal scan wire is spaced apart and electrically connected to the vertical scan wire, with the common electrode's projection covering the vertical scan wire's projection on the substrate, reducing parasitic capacitance and crosstalk.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the gate driver is integrated in a thin film flip-chip package on the display panel to reduce bezel width, then the bezel width is reduced, but parasitic capacitance between the scan wire and pixel electrode increases causing crosstalk

Engineering Contradiction:
Improvebezel widthVSAvoidcrosstalk
Core Design Contradiction:
Length of stationary objectVSObject-affected harmful factors

Solution Approach 1:

A shielding structure is introduced as an intermediary element between the scan wire and pixel electrode. This shielding structure acts as a mediator that blocks the harmful electromagnetic coupling between these two conductors, thereby reducing parasitic capacitance and crosstalk while allowing the integrated gate driver design to maintain its narrow bezel advantage

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the scan wire extends vertically in the pixel to connect the gate driver, then the gate driver integration is achieved, but parasitic capacitance is formed between the scan wire and pixel

Engineering Contradiction:
Improvegate driver integrationVSAvoidsignal integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The shielding structure serves as a mediator that preserves the integrated gate driver design while protecting signal integrity. By positioning the shielding structure between the scan wire and pixel electrode, it mediates the electromagnetic interaction to prevent harmful coupling without disrupting the functional connectivity of the integrated driver

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-affected harmful factors

If the common electrode layer is positioned away from the substrate to reduce parasitic capacitance, then crosstalk is reduced, but the structural complexity increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidlayer structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The common electrode layer is designed to serve multiple functions: it acts as both the common electrode for the liquid crystal display and as a shielding structure to reduce parasitic capacitance. This multi-functionality approach reduces structural complexity by eliminating the need for separate shielding layers while still achieving crosstalk reduction

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration minimizes parasitic capacitance between the vertical scan wire and pixel electrode, reducing crosstalk and improving display effect by shielding the pixel electrode from interference, thereby enhancing image quality.

Implementation Method 1

an orthographic projection of the common electrode on the substrate at least partially covers an orthographic projection of the vertical scan wire on the substrate

Methodology Applied
Scientific EffectElectrostatic shielding: Faraday Cage

Data Source

PatentUS20240072067A1Array substrate and display panel
Publication Date: 2024.02.29 SUZHOU CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US20240072067A1 patent drawing
  • US20240072067A1 patent drawing
  • US20240072067A1 patent drawing

AI summary

An array substrate and a display panel are disclosed. The array substrate includes a substrate, a scan wiring layer, and a common electrode layer. The scan wiring layer includes a vertical scan wire. The common electrode layer includes a common electrode and a horizontal scan wire. The horizontal scan wire is spaced apart from the common electrode. An orthographic projection of the common electrode on the substrate at least partially covers an orthographic projection of the vertical scan wire on the substrate.