3D SoC Face-to-Face Hybrid Bonding for Timing-Closed Interconnects
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Solution Overview
Problem
Current technologies face challenges in efficiently stacking Systems on Chip (SoCs) in three dimensions using face-to-face hybrid bonding, which is essential for achieving high-density, high-bandwidth interconnects for applications like augmented and virtual reality.
Innovation Solution
The proposed solution involves a semiconductor device with a first die and a second die, each including driver and load gates connected via via ladders to top metal layers. These dies are stacked three-dimensionally using face-to-face hybrid bonds, enabling signal driving in both directions and implementing three-dimensional interconnects that correctly close timing at the SoC level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacking of SoCs is implemented using conventional bonding methods, then device integration density is improved, but manufacturing complexity and precision requirements increase significantly
Solution Approach 1:
The patent transitions from conventional two-dimensional planar bonding to three-dimensional face-to-face hybrid bonding, where metal layers from opposite sides of the bonding interface are bonded together. This dimensional change enables higher integration density by stacking dies vertically while maintaining manageable manufacturing precision through the symmetric face-to-face approach.
Solution Approach 2:
The patent employs hybrid bonding that combines different bonding mechanisms (direct metal-to-metal bonding with copper-copper bonding and dielectric-to-dielectric bonding) to create a composite bonding interface. This composite approach allows simultaneous achievement of high integration density and reduced manufacturing precision requirements by distributing the bonding function across multiple material interfaces.
2Speed
If face-to-face hybrid bonding is used to stack dies, then interconnect bandwidth is improved, but timing closure complexity increases
Solution Approach 1:
The patent segments the interconnect structure into via ladders on each die that connect to corresponding via ladders on the opposing die through the face-to-face hybrid bonding interface. This segmentation allows independent optimization and timing closure of each segment while achieving high overall bandwidth through the parallel interconnect paths enabled by the three-dimensional stacking.
Data Source
AI summary
A method for three-dimensionally stacking systems on chip with face to face hybrid bonding may include providing a first die including a driver gate driving a first via ladder coupled to a first top metal layer. The method may additionally include providing a second die including a load gate coupled to a second via ladder coupled to a second top metal layer. The method may also include stacking the first die and the second die three-dimensionally using face-to-face hybrid bonds to couple the first top metal layer to the second top metal layer. Various other methods, systems, and computer-readable media are also disclosed.