3D Memory Cell Stacking With Misalignment-Tolerant Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in constructing 3D stacked semiconductor chips with high-density connections between layers due to issues such as incompatible processing temperatures for transistors and wiring, misalignment during wafer bonding, and limited contact density.
Innovation Solution
The development of methods to construct high-performance transistors at temperatures below 400°C, fabricate transistors in patterns that allow for high-density connectivity despite wafer misalignment, and design chip architectures where increased processing temperatures for top-layer transistors do not degrade bottom transistors and wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed at high temperatures (>700°C) to achieve high performance, then transistor performance is improved, but bottom wiring layers are damaged
Solution Approach 1:
The patent divides the semiconductor structure into separate stacked layers: bottom transistor layers formed at high temperatures, intermediate wiring layers formed at lower temperatures, and top transistor layers formed at intermediate temperatures. This segmentation allows each layer to be processed at optimal temperatures without damaging other layers, resolving the contradiction between high-performance transistor fabrication and wiring layer protection.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical stacking, arranging transistor layers and wiring layers in different vertical dimensions. This dimensional change enables independent temperature processing of different layers, allowing high-temperature transistor fabrication without damaging lower-temperature wiring layers that are spatially separated in the vertical dimension.
2Productivity
If wafer bonding is performed to stack multiple layers, then 3D integration is achieved, but misalignment occurs between layers
Solution Approach 1:
The patent forms alignment marks on the bottom substrate before bonding operations. These pre-formed marks serve as reference features that guide subsequent layer alignment during bonding processes, enabling precise registration of stacked layers and reducing misalignment errors.
Solution Approach 2:
The patent introduces alignment marks as intermediary reference features between the bonding surfaces of stacked wafers. These marks act as mediators that facilitate accurate alignment by providing visible registration targets, thereby improving manufacturing precision without compromising 3D integration density.
3Manufacturing precision
If contact size is increased to improve alignment tolerance, then misalignment issues are reduced, but contact density decreases
Solution Approach 1:
The patent moves contact formation from 2D planar arrangement to 3D vertical stacking, where contacts are distributed across multiple stacked layers. This dimensional transition allows smaller contact sizes while maintaining high connectivity through increased layer count, simultaneously improving alignment tolerance and preserving contact density.
Solution Approach 2:
The patent implements a nested hierarchical structure where multiple layers of transistors and wiring are stacked vertically, with contacts forming a 3D network through the layers. This nesting approach enables high-density interconnections by utilizing vertical space, allowing smaller individual contacts while achieving overall high contact density through multi-layer integration.
Data Source
AI summary
A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.