3D CMOS Layer Stacking With Shared Gates for Higher Density
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high device density per substrate unit area due to the stacking of NMOS and PMOS transistors, which limits their layout flexibility and efficiency.
Innovation Solution
A semiconductor device design that alternately stacks three or more layers of NMOS and PMOS transistors, with a gate electrode commonly connected across layers, enhancing device density and layout freedom by optimizing the stacking configuration and wiring connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NMOS and PMOS transistors are stacked in three-dimensional circuits, then device integration is achieved, but device density per substrate unit area remains small
Solution Approach 1:
The patent transitions from conventional planar or simple vertical stacking to a multi-layer three-dimensional stacking architecture where first and second semiconductor layers are stacked alternately. This multi-dimensional arrangement allows multiple transistors to be integrated within a compact footprint, significantly increasing device density per substrate unit area while managing complexity through systematic layering.
Solution Approach 2:
The patent implements nested stacking where transistor components are arranged in concentric or interlocked patterns across multiple layers. The first semiconductor layer containing first transistors and the second semiconductor layer containing second transistors are nested vertically, with shared substrates and interlayer connections that maximize space utilization and achieve high device density.
2Adaptability or versatility
If conventional transistor stacking is used, then integration is achieved, but layout flexibility is limited
Solution Approach 1:
The patent divides the semiconductor structure into distinct first and second semiconductor layers, each containing multiple transistors that can be independently configured. This segmentation allows flexible layout design within each layer while maintaining high overall density, enabling adaptability in circuit design and transistor arrangement patterns.
Solution Approach 2:
The patent creates a universal stacking architecture where the same structural framework supports both first transistors in the first semiconductor layer and second transistors in the second semiconductor layer. This multi-functional design allows the same substrate and interlayer connection structures to serve multiple transistor types, enhancing layout flexibility without sacrificing device density.
Data Source
AI summary
A semiconductor device according to embodiments includes: a first semiconductor layer having a first source region, a first drain region, and a first channel region; a second semiconductor layer having a second source region, a second drain region, and a second channel region; and a gate electrode that is formed to cover the first channel region and the second channel region with a gate insulating film interposed. The semiconductor device includes a first CMOS circuit and a second CMOS circuit each formed of the combination of a first conductive type MOS having the first semiconductor layer and a second conductive type MOS having the second semiconductor layer. The first semiconductor layer is stacked in a (2n−1)th layer. The second semiconductor layer is stacked in a 2nth layer (1≤n≤N, N≥2, and n and N are integers).