Stacked Folded Memory Bit-Cell Layout for Charge Disturbance Reduction
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Solution Overview
Problem
Current non-volatile memories, such as ferroelectric memories, suffer from charge degradation and disturbance due to the routing configuration of plate-lines relative to bit-lines and word-lines, leading to polarization decay and leakage, which affects data retention and reliability.
Innovation Solution
The implementation of a stacked and folded capacitor configuration with word-line boosting and refresh mechanisms, including wear leveling schemes and error correction, to mitigate charge disturbance and enhance memory endurance, while also optimizing capacitor placement to reduce parasitic capacitance and improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plate-lines are routed relative to bit-lines and word-lines in conventional configurations, then memory operations can be performed, but charge degradation and disturbance occur leading to polarization decay and leakage
Solution Approach 1:
The patent implements a stacked capacitor configuration where capacitors are arranged in vertical layers rather than planar arrangements. This dimensional change separates the plate-line routing from the bit-line and word-line planes, reducing parasitic capacitance and charge disturbance between adjacent lines while maintaining memory operation functionality.
Solution Approach 2:
The memory array is divided into multiple stacked capacitor layers, with each layer containing segmented capacitor elements. This segmentation allows independent optimization of each layer's routing configuration, reducing charge disturbance between adjacent bit-lines and word-lines while maintaining overall memory functionality.
2Reliability
If multiple capacitors are used in memory bit-cells, then data retention and reliability improve, but capacitor placement complexity and parasitic capacitance increase
Solution Approach 1:
Multiple capacitors are merged into a stacked configuration where they share common electrodes and routing structures. This combining approach maintains the reliability benefits of multiple capacitors while reducing placement complexity through standardized vertical stacking patterns and shared interconnect structures.
Solution Approach 2:
Multiple capacitors are arranged in the vertical dimension through stacking rather than lateral placement. This dimensional transition simplifies routing by allowing vertical interconnects and reduces parasitic capacitance between capacitors by increasing their spatial separation in the vertical direction.
3Ease of manufacture
If conventional capacitor configurations are used, then manufacturing is simpler, but parasitic capacitance causes charge leakage and reduced memory endurance
Solution Approach 1:
The capacitor configuration transitions to a stacked vertical arrangement that maintains compatibility with conventional planar manufacturing processes while adding the vertical dimension. This allows existing fabrication techniques to be used with minimal modification while achieving reduced parasitic capacitance through increased vertical separation between capacitor elements.
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.