Staggered Base Contact Layout for Memory Alignment

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Solution Overview

Problem

As feature dimensions in memory devices decrease to increase memory array densities, reliably connecting base and electrode components becomes challenging due to stringent tolerances, leading to potential misalignment and shorting issues in STI topologies.

Innovation Solution

The solution involves staggering base contacts and increasing the length dimension of base interconnect areas, along with using a pattern of alternating base interconnect areas along word-lines to reduce misalignment risks and electrical resistance, while maintaining adequate connections between electrodes and base components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If feature dimensions are decreased to increase memory array densities, then storage density is improved, but manufacturing precision and reliability deteriorate due to stringent tolerances and misalignment risks

Engineering Contradiction:

Improvememory array densityVSAvoidalignment precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent extends the base interconnect area in the lateral dimension (increasing length dimension) to provide a larger overlap area with the electrode. This dimensional extension compensates for the reduced tolerance margins caused by smaller feature dimensions, allowing for misalignment without causing shorting issues between adjacent structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a staggered pattern where base contacts and electrode connections are offset from each other. This segmentation in the layout pattern ensures that even with dimensional variations, the staggered arrangement prevents direct alignment that could cause shorting, while the extended interconnect areas ensure adequate electrical connection.

Inventive Principle:

Principle #1Segmentation

2Reliability

If base interconnect area length is increased to reduce misalignment risks, then connection reliability is improved, but device area increases

Engineering Contradiction:

Improveconnection reliabilityVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies the extended interconnect area strategy locally at critical connection points where base contacts meet electrodes, rather than uniformly increasing all dimensions. The staggered pattern concentrates the additional area where it is most needed for reliability, while maintaining compact dimensions in non-critical regions.

Inventive Principle:

Principle #3Local quality

3Reliability

If staggered base contact pattern is used to reduce shorting risks, then manufacturing robustness is improved, but layout complexity increases

Engineering Contradiction:

Improveshorting preventionVSAvoidlayout complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs an asymmetric staggered pattern where base contacts are deliberately offset from electrode centers. This asymmetric arrangement breaks the symmetry that would otherwise cause direct alignment and potential shorting, while the pattern remains systematic and manufacturable through standard photolithography processes.

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS9786719B2Method for base contact layout, such as for memory

Publication Date: 2017.10.10 MICRON TECHNOLOGY INC

AI summary

Embodiments disclosed herein may relate to forming a base contact layout in a memory device.