Array Substrate Gate Insulator Layout for TFT Drive and Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing organic light-emitting display panel structure makes it difficult to simultaneously optimize the driving capability of the driving transistor and the control capability of the switching transistor due to their shared gate insulating layer structure and thickness.
Innovation Solution
The array substrate design includes a thin film transistor array layer with a driving transistor and a switching transistor, where the first gate insulating layer of the driving transistor is thicker than the second gate insulating layer of the switching transistor, allowing for different gate capacitances and subthreshold swings, enabling simultaneous optimization of driving and switching capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating layer thickness is increased to improve driving capability, then the driving capability of the driving transistor is improved, but the control capability of the switching transistor deteriorates
Solution Approach 1:
The gate insulating layer is segmented into two distinct layers: a first gate insulating layer for the driving transistor and a second gate insulating layer for the switching transistor. This allows each transistor to have independently optimized gate insulating layer thickness, enabling the driving transistor to have a thicker layer for better driving capability while the switching transistor has a thinner layer for better control capability.
Solution Approach 2:
Different regions of the gate insulating structure are assigned different thicknesses based on local requirements. The first gate insulating layer has a greater thickness specifically at the driving transistor region to enhance driving capability, while the second gate insulating layer has a smaller thickness at the switching transistor region to improve control capability,实现ing localized optimization without compromising overall device performance.
2Ease of manufacture
If the gate insulating layer thickness is uniform to simplify manufacturing, then manufacturing complexity is reduced, but the ability to simultaneously optimize driving and switching performance deteriorates
Solution Approach 1:
The gate insulating layer is divided into two separately formed layers, allowing independent thickness control for each transistor type. This segmentation enables simultaneous optimization of driving and switching performance while maintaining a systematic manufacturing approach where each layer can be processed according to its specific requirements.
Solution Approach 2:
The thickness parameter of the gate insulating layer is changed differently for the two transistor types. The first gate insulating layer is formed with a greater thickness for the driving transistor, while the second gate insulating layer is formed with a smaller thickness for the switching transistor, allowing each transistor to operate at its optimal performance point.
Data Source
AI summary
An array substrate and a display panel. The array substrate includes a thin film transistor array layer including a driving transistor, a switching transistor, and a capacitor. The driving transistor includes a first active layer, a first gate insulating layer, a first gate, and an insulating dielectric layer sequentially stacked. The switching transistor includes a second active layer, a second gate insulating layer, and a second gate sequentially stacked. The insulating dielectric layer and the second gate insulating layer are located at a same layer. A thickness of the first gate insulating layer is greater than a thickness of the second gate insulating layer. The capacitor includes a first electrode plate and a second electrode plate. The first electrode plate and the first gate are disposed on same layer, and the second electrode plate and the second gate are disposed on same layer.