Tapered Isolation Trenches for Dense High-Voltage Memory Periphery
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to reduce the number of fabrication steps and scale components smaller to increase device density within a given area, while also addressing different voltage needs for peripheral circuitry and memory arrays efficiently.
Innovation Solution
The use of isolation trenches with tapered sidewalls that intersect along a line at a trench bottom, allowing for increased isolation without flattening the bottom, enables the formation of components on pitch with the memory array, enabling efficient fabrication and high device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation trenches with flat bottoms are used to provide electrical isolation, then isolation effectiveness is improved, but fabrication complexity and number of steps increase
Solution Approach 1:
Instead of creating a flat-bottomed trench through complex multi-step etching processes, the patent inverts the approach by creating a tapered trench with a pointed bottom and then filling it with dielectric material. The fill process naturally creates the effective isolation barrier without requiring precise flat-bottom formation, thus simplifying fabrication while maintaining isolation effectiveness.
Solution Approach 2:
The patent changes the geometric parameters of the isolation trench from a traditional flat-bottomed cylindrical shape to a tapered shape with a pointed bottom. This parameter change allows the trench to be formed through simpler single-step or reduced-step etching processes, reducing fabrication complexity while the subsequent dielectric fill maintains the electrical isolation function.
2Productivity
If component size is reduced to increase device density, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating isolation trenches with tapered sidewalls that provide varying widths at different depths. The narrower upper portion provides effective isolation where needed, while the tapered geometry allows for relaxed precision requirements during etching compared to maintaining a uniformly narrow flat-bottomed trench throughout.
Solution Approach 2:
The isolation structure is segmented into the tapered trench portion and the dielectric fill portion. This segmentation allows each part to be optimized independently - the tapered trench provides structural definition with relaxed precision requirements, while the dielectric fill provides the actual isolation function, collectively achieving high device density without excessive manufacturing precision demands.
3Power
If peripheral circuitry operates at higher voltages to improve performance, then operational capability is improved, but electrical isolation requirements increase
Solution Approach 1:
The patent uses composite structures by combining the tapered silicon dioxide trench with an additional dielectric material fill. This composite isolation structure provides enhanced electrical isolation capability that can effectively contain higher voltage peripheral circuitry, preventing voltage breakdown while maintaining the benefits of the tapered geometry.
Solution Approach 2:
The dielectric fill material acts as a cushioning layer that provides additional electrical isolation margin before voltage breakdown can occur. This beforehand cushioning allows the peripheral circuitry to operate at higher voltages by providing a safety margin that prevents electrical breakdown, thus supporting improved operational capability while maintaining isolation reliability.
Data Source
AI summary
Apparatus and methods are disclosed, including transistors, semiconductor devices and systems with isolation structures. Example semiconductor devices and methods include isolation structures with tapered sidewalls that intersect along a line at a trench bottom. Example semiconductor devices and methods are shown with different isolation structures in peripheral circuitry compared to isolation structures in a memory array.