3D Semiconductor Package Bias Plates for Reliable Well Biasing
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Solution Overview
Problem
As the degree of integration in semiconductor devices increases, the decreasing gap between wires for voltage and current signal input/output complicates reliable power delivery and signal transmission, degrading system performance and limiting further integration.
Innovation Solution
A semiconductor device with a three-dimensional stack structure and patterned bias voltage plates on substrates, utilizing through contact plugs to apply well bias voltages and back bias voltages efficiently, enhancing the design margin of wiring and ensuring reliable bias voltage provision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration in semiconductor devices is increased, then the functionality and capacity of the device are improved, but the gap between wires decreases making reliable power delivery and signal transmission more difficult
Solution Approach 1:
The patent introduces a third dimension by forming bias voltage plates on the back surface of the substrate, perpendicular to the conventional planar wiring layer. This vertical stacking approach allows bias voltage application without occupying lateral wiring space, enabling higher integration while maintaining reliable power delivery through the substrate thickness dimension.
Solution Approach 2:
The bias voltage plate is segmented into multiple regions that can be independently connected to different well regions or substrates. This segmentation allows selective biasing of different device regions, improving power delivery reliability for high-density integrated circuits by providing localized voltage control.
2Area of stationary object
If the wiring gap is decreased to increase integration, then more components can be packed, but providing power reliably and transmitting signals correctly becomes more difficult
Solution Approach 1:
By moving the bias voltage application point from the lateral wiring plane to the vertical substrate back surface, the patent eliminates the need for closely spaced bias voltage wires. This dimensional shift maintains signal transmission reliability while allowing minimal lateral wiring gaps for high-density integration.
3Device complexity
If conventional planar wiring is used, then the structure is simple, but the design margin of wiring is limited and bias voltage provision becomes unreliable at high integration
Solution Approach 1:
The patent adds a vertical dimension by placing bias voltage plates on the substrate back surface, creating a three-dimensional wiring architecture. This maintains relative structural simplicity while dramatically improving bias voltage provision reliability for high-density integrated circuits by separating bias voltage delivery from lateral signal wiring.
Data Source
AI summary
A semiconductor device includes a first substrate including at least one first well region and first impurity regions on portions of the substrate and a bias voltage plate on a surface of the substrate. A semiconductor device may be of a three dimensional stack structure, and in example embodiments, the semiconductor device may further include a through contact plug substantially perpendicularly penetrating at least one substrate and at least one bias voltage plate. Therefore, a design margin of a semiconductor device may be enhanced and a bias voltage may be provided reliably.