3D Capacitor Electrode Structure for Higher Capacitance Scaling
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Solution Overview
Problem
Semiconductor devices face challenges in scaling down while maintaining quality, yield, performance, and reliability due to issues such as reduced complexity and capacitance in capacitor structures.
Innovation Solution
A semiconductor device design featuring a substrate with a bottom conductive layer, bottom conductive protrusions, an insulator layer, and a top conductive layer, along with bottom and top insulating protrusions, which increases the contact surface area between electrodes, thereby enhancing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to meet increasing computing demand, then device density and computing ability are improved, but capacitance and performance of capacitor structures deteriorate
Solution Approach 1:
The capacitor structure is segmented into multiple components: a bottom electrode with protrusions, a top electrode with protrusions, and an insulator layer with protrusions. This segmentation creates multiple contact interfaces between electrodes and insulator, effectively increasing the total capacitance despite the overall device size reduction
Solution Approach 2:
The invention transitions from a planar capacitor structure to a three-dimensional structure with protrusions extending vertically and horizontally. The bottom electrode protrusions extend upward, the top electrode protrusions extend downward, and insulator protrusions extend between them, creating multiple overlapping contact areas that increase capacitance in the vertical dimension
2Length of moving object
If device dimensions are reduced, then device size is improved, but contact surface area between electrodes deteriorates
Solution Approach 1:
The electrode and insulator structures incorporate curved protrusions rather than sharp angular features. The bottom electrode protrusions have curved top surfaces, the top electrode protrusions have curved bottom surfaces, and insulator protrusions have curved interfaces, increasing the effective contact surface area through geometric curvature
Solution Approach 2:
The protrusions are nested within each other's spatial envelope: bottom electrode protrusions extend into the insulator layer, top electrode protrusions extend into the insulator layer from the opposite side, and insulator protrusions are positioned between them. This nesting creates multiple overlapping contact zones that maximize surface area within a compact footprint
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive layer positioned on the substrate; at least one bottom conductive protrusion positioned on the bottom conductive layer; an insulator layer positioned on the bottom conductive layer and the at least one bottom conductive protrusion; at least one bottom insulating protrusion protruding from the insulator layer towards the bottom conductive layer and adjacent to the at least one bottom conductive protrusion; and a top conductive layer positioned on the insulator layer. The bottom conductive layer, the at least one bottom conductive protrusion, the insulator layer, the at least one bottom insulating protrusion, and the top conductive layer together configure a capacitor structure.