3D Integrated Capacitor Structure for High-Density Decoupling
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Solution Overview
Problem
Conventional capacitors in semiconductor chips and substrates face limitations in high capacitance density and efficiency, particularly in decoupling applications, with planar capacitors having low capacitance and high impedance, and silicon capacitors lacking sufficient current storage capacity.
Innovation Solution
The development of capacitors with electrodes and conductive plates integrated into a substrate with a low coefficient of thermal expansion, utilizing dielectric layers and conductive elements within openings in the substrate to enhance capacitance and reduce inductance, including three-dimensional configurations and undulating dielectric shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar capacitors with thin dielectric materials are used, then the dielectric constant is very high, but the capacitance density is low and the quality factor is low
Solution Approach 1:
The patent transitions from planar two-dimensional capacitor structures to three-dimensional vertically stacked capacitor structures. Multiple capacitor layers are stacked vertically within the same footprint area, dramatically increasing capacitance density while maintaining or improving quality factor through optimized dielectric material selection and reduced parasitic inductance from vertical current paths.
Solution Approach 2:
The patent employs composite dielectric materials with high dielectric constants (k > 3) such as barium strontium titanate (BST) or other ferroelectric materials combined with conductive layers. This composite structure enables both high capacitance density and high quality factor by selecting materials with complementary properties for each layer.
2Reliability
If multiple capacitors are mounted along the power line for noise suppression, then the noise suppression performance is improved, but the system size and cost increase
Solution Approach 1:
The patent integrates multiple capacitor functions into a single integrated capacitor structure. By stacking multiple capacitor layers with different dielectric materials and configurations within one component, the device provides enhanced noise suppression across multiple frequency ranges without requiring multiple separate capacitor components, thereby reducing system size and simplifying mounting.
Solution Approach 2:
The integrated capacitor structure serves multiple decoupling functions simultaneously. Different capacitor layers are optimized for different frequency ranges, allowing a single component to perform both low-frequency and high-frequency noise suppression that would traditionally require multiple separate capacitors mounted along the power line.
3Quantity of substance
If DRAM-level capacitors are used for high capacitance applications, then the capacitor size is very small, but the current storage and supply capability is insufficient
Solution Approach 1:
The patent divides the capacitor structure into multiple functional segments or layers, each optimized for specific performance characteristics. By segmenting the capacitor into multiple stacked layers with different dielectric materials and electrode configurations, the design achieves both high total capacitance and high current supply capability, as each layer contributes to the overall power delivery capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high capacitance density and reduced inductance, resulting in improved noise suppression and compact system design with reduced material and manufacturing costs.
Implementation Method 1
The first and second pairs of plates can be separated from at least one adjacent plate by a dielectric layer. Each dielectric layer separating each of the plates from the at least one adjacent plate can be a dielectric layer having a dielectric constant k of at least 3.
Implementation Method 2
The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C.
Implementation Method 3
The first capacitor can include at least first and second pairs of electrically conductive plates connectable with respective first and second electric potentials. The first capacitor can include first and second electrodes.
Data Source
AI summary
A component includes a substrate and electrically conductive layers formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The electrically conductive layers can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.