3D Capacitor Structure Reducing Series Resistance
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Solution Overview
Problem
Existing capacitor structures with high capacitor surface-density suffer from high equivalent serial resistance, limiting their electrical performance, especially at high frequencies, and are costly to manufacture.
Innovation Solution
A 3D-capacitor structure is designed on a silicon substrate with a trench extending from the top face, featuring multiple trench portions, layer-shaped electrodes, and dielectric-electrode structures, along with conductive tracks and contact pads to reduce equivalent serial resistance and inductance, while maintaining high surface-density and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If surface-mounted components are used externally with long interconnection paths, then capacitor surface-density is increased, but equivalent serial resistance and equivalent serial inductance become significant
Solution Approach 1:
The patent transitions from 2D surface-mounted capacitors to 3D integrated capacitors by etching trenches into the substrate and stacking multiple capacitor layers vertically. This dimensional change reduces interconnection path length while maintaining high capacitor surface-density, thereby reducing equivalent serial resistance and inductance.
Solution Approach 2:
The patent embeds multiple capacitor layers within a single substrate by creating trenches and stacking dielectric and electrode layers vertically. This nesting approach increases capacitor surface-density without increasing the lateral footprint, and reduces connection length to the power supply grid.
2Quantity of substance
If capacitor layer stack covers sidewalls of pillar in trench, then capacitor surface-density increases, but equivalent serial resistance becomes high
Solution Approach 1:
The patent divides the trench into multiple sections separated by not-etched areas, with each section containing capacitor layers. This segmentation allows for optimized electrode routing and reduced series resistance while maintaining high capacitor surface-density through the vertical stacking.
Solution Approach 2:
The patent introduces conductive tracks as intermediary elements that connect the stacked capacitor layers to external terminals. These tracks provide low-resistance pathways for current flow, reducing the equivalent serial resistance while allowing the capacitor layers to maintain high surface-density coverage.
3Ease of manufacture
If trench openings and via openings are formed with same lateral extent, then fabrication cost is reduced, but equivalent serial resistance remains high
Solution Approach 1:
The patent varies the lateral extent of different openings in the substrate: trench openings have a first lateral extent for capacitor layer formation, while via openings have a second lateral extent for electrode connection. This local differentiation optimizes both fabrication efficiency and electrical performance by reducing equivalent serial resistance through properly sized connection pathways.
Data Source
AI summary
A capacitor 3D-cell formed on a silicon substrate is designed for producing low equivalent serial resistance and high capacitor surface-density. It combines a trench capacitor structure, multiple contact pads to at least one of the electrodes and a track which connects the electrode through the multiple contact pads so as to bypass said electrode between trench portions which are located apart from each other.