3D Capacitor Support Pads for DRAM Edge Collapse
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Solution Overview
Problem
In semiconductor devices, particularly dynamic random access memory (DRAM) devices, maintaining sufficient capacitance within a limited area is challenging due to the need for increased integration densities, and existing methods to enhance the effective area of lower electrodes, such as cylindrical or stack type electrodes, face issues with collapse or tearing at cell block edges.
Innovation Solution
The implementation of three-dimensional capacitors with cylindrical lower electrodes, dielectric layers, and capacitor support pads made of materials with tensile stress greater than a predetermined value and resistant to wet etching, such as carbon-doped silicon nitride layers, to reduce collapse and tearing at cell block edges, while maintaining symmetry and uniformity in dielectric layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cylindrical or stack type lower electrodes are used to increase effective area, then capacitance is improved, but collapse or tearing occurs at cell block edges
Solution Approach 1:
Mold oxide layers are formed in advance around the lower electrodes to provide structural support before the electrodes are fully formed and before any collapse can occur. This preliminary structural framework prevents tearing at cell block edges during subsequent processing steps.
Solution Approach 2:
The mold oxide layer acts as an intermediary structural element between the lower electrode and the surrounding environment. It provides mechanical support to the thin-walled lower electrode, preventing collapse while allowing the electrode to maintain its high surface area geometry for sufficient capacitance.
2Reliability
If heights of lower electrodes are increased to ensure sufficient capacitance, then capacitance is improved, but manufacturing complexity increases
Solution Approach 1:
Cylindrical or stack-type lower electrodes with curved surfaces are used instead of flat planar electrodes. This curvature increases the surface area (and thus capacitance) within the same footprint without requiring excessive height, simplifying the overall device structure while meeting capacitance requirements.
3Reliability
If three-dimensional capacitors are used to increase effective area, then capacitance is improved, but uniformity and symmetry in dielectric layer formation becomes difficult
Solution Approach 1:
Mold oxide layers are formed in advance around the lower electrodes to create a standardized geometric template. This preliminary structure guides subsequent dielectric layer deposition, ensuring uniform thickness and symmetric coverage even on three-dimensional electrode surfaces, thereby maintaining manufacturing precision while achieving high capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the effective area of lower electrodes, reduces tearing and collapse at cell block edges, and ensures uniform and symmetric deposition of subsequent materials, thereby enhancing the electrical characteristics and reliability of semiconductor devices.
Implementation Method 1
capacitor support pads made of materials with tensile stress greater than a predetermined value
Implementation Method 2
resistant to wet etching, such as carbon-doped silicon nitride layers
Data Source
AI summary
A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.