3D CCD Memory Read-Out Scheme for Scalable Low-Power SCM
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Solution Overview
Problem
The gap between low-cost storage memory and high-speed working memory is significant due to the mismatch between increasing data demands and conventional memory technologies, with existing storage class memories lacking scalability, power efficiency, or cycling capability.
Innovation Solution
An integrated 3D charge-coupled device (CCD) memory architecture with a high-density memory array and efficient read-out scheme, utilizing a layer stack of gate and spacer layers, semiconductor-based channels, and charge sensing circuits to achieve high memory cell density, scalability, and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM is used to bridge the memory gap, then high-speed working memory performance is achieved, but scalability is limited due to the approaching scaling brick wall
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertical stacking architecture. Multiple memory layers are stacked along the vertical direction, with each layer containing memory cells formed by intersections of bit lines and word lines. This 3D configuration enables continued scaling of memory capacity without increasing the planar footprint, effectively overcoming the scaling limitations of conventional DRAM while maintaining high-speed performance characteristics.
2Adaptability or versatility
If phase change memory is used for storage class memory, then scalability is improved, but power efficiency deteriorates
Solution Approach 1:
The patent replaces the phase change mechanism (thermal field) with a charge-based memory mechanism (electrical field). Instead of using phase change materials that require thermal energy for state transitions, the invention uses floating diffusion regions that store electrical charge. This substitution eliminates the high power consumption associated with phase change memory while maintaining scalability through the 3D vertical architecture.
3Use of energy by moving object
If magnetic random access memory is used for storage class memory, then power efficiency is improved, but cycling capability deteriorates
Solution Approach 1:
The patent replaces the magnetic field mechanism with an electrical charge-based mechanism. Instead of using magnetic domains that require magnetic field switching, the invention uses floating diffusion regions that store and transfer electrical charge. This substitution provides nearly unlimited read/write cycling capability similar to conventional DRAM, while maintaining the low power consumption characteristics of storage class memory through the non-volatile nature of the charge storage.
4Reliability
If low-latency NAND memory is used for storage class memory, then cycling capability is improved, but power efficiency deteriorates
Solution Approach 1:
The patent uses vertical stacking to achieve high density while maintaining fast access characteristics. The 3D architecture with multiple layers allows parallel access to different memory banks, reducing latency. The charge-based mechanism provides low power consumption compared to NAND flash, while the vertical architecture enables scaling similar to high-capacity storage devices.
5Ease of operation
If byte-addressability is maintained in CCD-based memory, then memory access flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional approach by not implementing byte-addressability in CCD-based memory. Instead of forcing CCD technology to conform to conventional RAM addressing schemes, the invention accepts block-addressability as the native interface. This inversion simplifies the manufacturing process and device architecture while still providing useful memory functionality for applications that can operate with block-level access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D CCD memory provides high memory cell density, good reliability, nearly unlimited cycling, and low power consumption, enabling efficient read-out operations through a correlated double sampling scheme.
Implementation Method 1
configured to translate charge in the floating diffusion of the at least one CCD register into a voltage on an associated column line
Data Source
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AI summary
The present disclosure relates to a three-dimensional (3D) integrated CCD memory, for instance, a storage class memory (SCM). The CCD memory comprises a layer stack including a plurality of gate layers and spacer layers alternatingly arranged one on the other. The CCD memory further comprises a plurality of semiconductor-based channels extending in the stack, wherein the channels form, in combination with the gate layers and one or more gate dielectric layers, a plurality of strings of charge storage capacitors, which are operable as a plurality of CCD registers. An end of each CCD register is connected to a floating diffusion. The CCD memory further comprises a plurality of charge sensing circuits. Each charge sensing circuit is connected to the floating diffusion of at least one CCD register, and is configured to translate charge in the floating diffusion of the at least one CCD register into a voltage on an associated column line.