Digital Storage TRIZ Cases

A 3D CCD memory uses charge sensing and correlated double sampling to deliver scalable storage-class memory with low power and reliable cycling.

Shared global data lines and segmented memory banks raise capacity while shortening transmission paths to reduce signal errors.

Asymmetric source and drain structures lower electric field peaks in high-voltage FinFETs, improving HCI and GIDL reliability.

Connection cells and a common bit line rearrange 3D memory cells to reduce etch loading on selection transistors and improve yield.

By forming RRAM in the first local interconnect metal layer, this case avoids top-surface unevenness and removes extra planarization.

In-band MRUPD register writes speed DRAM and RCD training by avoiding slow sideband buses and reducing MPC command overhead.

Diode-limited delay elements adjust memory-array signal timing with VDD changes, improving cell-operation tracking without manual calibration.

A series variable element and oxide layer stabilize SET resistance, control current and voltage, and improve phase change memory endurance.

A ferromagnetic field element beside the MTJ boosts initial torque, cutting P-to-AP write latency and switching asymmetry in MRAM.

Segmented weight groups and differential ADCs distribute cell currents across bit lines to curb IR drop and preserve in-memory computing accuracy.

Multiple ferromagnetic strips with aligned notches and a spin-orbit coupling layer reduce domain-wall variation for more precise MTJ conductance programming.

A voltage-controlled protection transistor lets a low-voltage word line driver switch high word line voltages without SOA violations or added bias complexity.

By detecting the data strobe preamble, the circuit generates reset pulses that reduce timing variation and prevent memory interface errors.

Oxide semiconductor channel layers and a trimming insulating block curb DRAM leakage current and contact resistance while preserving dense integration.

Dual power switching lets a memory sense amplifier detect small read signals, then supply higher write-back voltage without exceeding thin-gate limits.

A configurable memory metadata portion stores host-supplied ECC alongside data, cutting SRAM overhead and simplifying multi-layer error protection.

Controlled first and second write voltages limit current in resistive memory arrays, cutting write energy and cell stress.

A control transistor creates a discharge path and manages voltage distribution to reduce dielectric stress and threshold drift in ferroelectric memory.

Incremental word, bit, and select voltage stepping programs crossbar RRAM within low-voltage transistor limits for compact arrays.

Host-generated ECC is stored in a configurable memory metadata portion, cutting SRAM cost and soft-error exposure while preserving error correction.

Timing check, delay, and XOR verification circuits keep multiple memories aligned to one clock, preventing timing conflicts and operation failures.

A series resistive memory and switching cell creates four programmable states, increasing non-volatile memory bit density without multiplying cells.

Flexible per-bank, quad-bank, and octa-bank refresh scheduling cuts memory latency by refreshing adjacent or spaced banks without stalling traffic.

Charge accumulation through FeFET-switched capacitors enables MAC operations with better variation resilience and lower energy than current-domain CiM.

Verification-data remapping lets a row decoder skip damaged memory blocks, improving memory yield without relying only on redundancy or ECC.

Adaptive per-bank, quad-bank, and octa-bank refresh cuts memory refresh latency and reduces traffic stalls by matching bank usage.

A vertical TFT with graded channel conductivity cuts contact resistance and raises on-state current for denser, faster memory.

Delaying the decoding clock after the CA clock aligns buffered command bits at the decoder, cutting memory power use and latency.

Parallel auxiliary transistors equalize MRAM bitline and source-line resistance, preserving read/write margins across cell location and temperature changes.

Switchable sense amplifier supplies enable subtle voltage sensing and high-voltage write-back without exceeding core device limits.

Sharing one phase decoder across adjacent memory sections cuts row decoder area, wiring burden, and DRAM power use while preserving timing balance.

Dual-edge sampling with a delay path helps DRAM command decoding and address output stay aligned when high-frequency 1N timing windows are tight.

CMOS logic placed under a memory array accumulates stored weights and compares them to a threshold to cut neural-network processing latency.

Shared bit and plate lines with a 1S1C stacked FRAM layout raise storage density while limiting crosstalk and process complexity.

Floating unselected word lines lets them track plate voltage, cutting parasitic cross-coupling, power loss, and memory data errors.

Aligned trench transistors and a cut channel plug raise non-volatile memory density while improving structural stability in 3D arrays.

Placing DRAM contact structures close to the connecting line reduces resistance mismatch and stabilizes bit line select transistor switching.

Voltage-driven oxygen ion migration flips spin-orbit torque polarity, cutting write-circuit complexity and power in dense non-volatile memory.

Weighted DQS calibration aligns rank signal timing across stacked memory dies to cut data collisions and improve bandwidth efficiency.

A replica bit line circuit drives both sense amplifier startup and negative write boosting, cutting separate control circuitry and area.

A stacked diode-connected suppressing circuit clamps word-line overvoltage to prevent bit flips without slowing memory operation.

Ramp-voltage comparison and pulse-duration encoding enable calibrated hardware activation functions with high accuracy and efficient neuromorphic inference.

Holding DRAM main I/O line states across write cycles cuts unnecessary resets, lowering current use, heat, and bus noise.

A feed-forward delay controller uses data toggle rates to correct strobe-data skew and keep memory writes within the valid timing window.

Monitor transistors sense DRAM storage node voltage through field effect, avoiding charge disruption while enabling in-situ cell behavior analysis.

Adjusted MOSFET control voltages keep DRAM bit lines near a target level during offset elimination, improving sensing under PVT variation.

Replacing costly platinum with TiN or TaN electrodes keeps RRAM analog behavior while improving CMOS compatibility and manufacturing cost.

Using the fiber core as a light-guided readback channel raises optical storage density and speed while avoiding wafer z-spacing and focusing limits.

A weak pre-sensing stage followed by stronger main sensing cuts DRAM LSA-to-BLSA leakage current while preserving fast sensing.

DAC-based word and bit line drivers let CAM cells store multi-bit values with n cells instead of 2n, reducing chip area and cost.

Segmented virtual ground control eliminates standby leakage currents while maintaining the I ON / I OFF ratio required for reliable data reading operations.

Write training measures data strobe delay variations caused by power supply voltage fluctuations to maintain synchronization.

A sense amplification unit adjusts precharge timing to optimize driving signals.

A charge retention circuit reads residual voltage using parallel branches and a comparator to enable accurate time measurement.

Clock control unit generates target frequency signals to evaluate high-speed characteristics using existing test equipment.

A multi-die memory package shares power resources through a common conductive path to coordinate operations across multiple devices.

A neural network device using four-gate non-volatile memory cells to store synapse weights via electron trapping on floating gates.

Dynamic voltage control reduces ripple and overshoot across varying loads, improving sensing margins in portable memory devices.

A cell voltage generator adjusts supply voltage levels to enhance write speed in memory arrays.

Distance detection circuits measure current travel to adjust auxiliary drivers, preventing incomplete crystallization in phase change memory cells.

Soft post package repair suspends non-maintenance requests to remap faulty rows, ensuring data integrity across system resets.

A DDR3 RDIMC circuit connects the clock enable input to a termination voltage source for stable self-refresh operation.

Separate contact sets allow pre-assembly probing without damaging mission-mode interconnections, improving multiple-die stack reliability.

A semiconductor memory device connects data input lines to bit lines via column selection transistors during specific time intervals.

A word line driver circuit uses a switching circuit to direct signals.

A signal line driver manages biasing signals using digital to analog converters and current sources.

Dual-mode clamp circuits stabilize memory module power during hot plug events, preventing overcurrent damage.

A shift register uses a pre-charging switch and level shifting mechanism to manage voltage levels.

Segmented shared match lines lower power consumption by charging fewer transistors while maintaining NOR-type search speed.

A DRAM amplifier circuit adjusts offset cancellation duration based on temperature sensing to optimize readout speed.

A reference voltage generation circuit uses capacitors to average voltages from reference bits.

A memory device generates an averaged reference voltage by shorting together reference nodes to determine an average of values associated with the reference nodes.

A semiconductor training device adjusts DQ signal delays to synchronize data output across multiple chips.

Pre-charge transistors set cell branch voltage before read operations, reducing stabilization time and spike currents below ten nanoseconds.

Head and foot switches disconnect memory cells and peripheral circuits during sleep mode, reducing leakage current while maintaining high integration density.

An inversion flag device inverts data bits to enable accurate reading from defective SpRAM cells.

Internal voltage generating circuit adjusts driving ability based on external power supply detection.

A resistive memory device employs a buffer array to hold data during drift stabilization, preventing read errors while maintaining compact size.

A latch circuit device captures input signals during microcomputer sleep periods to reduce occupied input ports.

Optimizes termination resistor values across ranks by varying activation timing relative to write latency, resolving impedance mismatch issues.

A stacked memory device consolidates spare cells into a unified system layer pool to manage logical replacements across multiple memory dies.

Parasitic capacitance between a dummy line and word-line boosts voltage above the supply rail, resolving write failures in scaled memory nodes.

Heusler alloy spin-transfer-torque magnetic tunnel junctions resolve high switching current and low tunnel magnetoresistance bottlenecks in flash memory.

Selection logic uses higher frequency memory command clock to reduce jitter and drift in DDR systems.

Segmenting the bit line isolates cutoff current from the main path, suppressing read margin degradation during cell miniaturization.

Segmented magnetic resistors store analog resistance values via domain-wall movement to enable efficient neuromorphic processing.

A hybrid memory circuit combines skewed static logic with dynamic pre-discharge devices to enable high-speed sensing operations.