Differential Bit-Line Memory Computing to Mitigate IR Drop
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Solution Overview
Problem
In-memory computing (IMC) faces significant voltage drops (IR drop) due to the accumulation of large cell currents, affecting accuracy during parallel processing.
Innovation Solution
A memory device architecture with summation groups, including first and second weight groups, global bit line pairs, and differential analog-to-digital converters (ADCs), where threshold voltages of memory cells form weights, generating input weight product currents that are processed by ADCs to output a product accumulation operation result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large amount of cell current is accumulated during parallel in-memory computing, then data processing speed is improved, but severe voltage drop occurs affecting computing accuracy
Solution Approach 1:
The bit line is divided into multiple segments (first bit line and second bit line) that are spatially separated. The first memory string pairs connect to the first bit line while the second memory string pairs connect to the second bit line, reducing current accumulation in any single bit line path and thereby minimizing voltage drop while maintaining parallel processing capability
Solution Approach 2:
The patent introduces a dimensional separation by providing multiple bit lines (first bit line and second bit line) in addition to the word lines and string select lines. This additional dimensional routing allows current to be distributed across multiple paths, reducing the IR drop effect in each individual path while preserving the parallel computing advantage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution mitigates voltage drops and enhances the accuracy of in-memory computing by effectively handling large cell currents, improving data processing efficiency.
Implementation Method 1
A plurality of threshold voltages of a plurality of memory cells of the first memory string pairs of the first weight group are combined to form a plurality of first weights
Implementation Method 2
a plurality of differential analog-to-digital converters (ADCs), each of the differential ADCs is coupled to a corresponding one of the global bit line pairs
Data Source
AI summary
The application discloses a memory device and a computation method. A first weight group generates a first input weight product current on a first global bit line basing on one of a plurality of inputs, and a second weight group generates a second input weight product current on a second global bit line basing on the one of the plurality of inputs. The first global bit line and the second global bit line output the first input weight product current and the second input weight product current to a first differential ADC. The first differential ADC outputs a product accumulation operation result basing on the first input weight product current and the second input weight product current.