Capacitive Compute-in-Memory Cell Using FeFET Weight Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current-domain CiM architectures face challenges in maintaining computational accuracy and efficiency due to sensitivity to device conductance variations, noise, and energy inefficiencies, particularly in multi-level conductance states.
Innovation Solution
A CiM architecture using nonvolatile memory transistors and capacitors in series, where FeFETs act as switches to control charge accumulation, enabling binary and multi-bit computations with improved resilience to device variation and reduced energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current-domain CiM architectures are used, then computational tasks can be performed within the memory array, but sensitivity to device conductance variations and noise reduces computational accuracy
Solution Approach 1:
The patent replaces current-domain computation with charge-domain computation. Instead of using current flow through conductive elements (analogous to mechanical systems susceptible to friction and wear), the invention uses charge accumulation on capacitive elements. This substitution eliminates sensitivity to conductance variations and noise, as charge storage is binary and stable, directly resolving the contradiction between computational throughput and accuracy.
Solution Approach 2:
The invention changes the fundamental operating parameter from current (continuous analog value susceptible to noise) to charge (discrete binary value with high stability). By programming FeFET threshold voltages to represent binary weights and using charge accumulation to represent computational results, the system achieves high computational accuracy while maintaining parallel processing capabilities for high throughput.
2Measurement precision
If multi-level conductance states are used, then more computational precision can be achieved, but sensitivity to device variations increases
Solution Approach 1:
Instead of using multi-level conductance states (continuous analog values) to represent weights, the invention inverts the approach by using binary FeFET threshold voltage states combined with charge accumulation levels. The FeFET is programmed to one of two threshold voltage states (binary weight), and the computational precision is achieved through the number of charge accumulation levels, which are controlled by the number of charging cycles rather than device conductance variations.
3Use of energy by moving object
If nonvolatile memory transistors are used, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The FeFET serves multiple functions: it acts as a nonvolatile memory element for storing binary weight values, as a switch for controlling charge transfer, and as a programmable device for configuring computational weights. The capacitor serves dual purposes as both charge storage for computational results and as part of the sensing circuitry. This multi-functionality reduces the need for separate dedicated components, offsetting the increased device complexity with functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed architecture enhances computational accuracy and energy efficiency by leveraging charge-based operations, reducing sensitivity to device-level variations and supporting high-density integration suitable for AI accelerators.
Implementation Method 1
The disclosed architecture can support binary and/or multi-bit computation and, in some cases, can utilize ferroelectric field-effect transistors (FeFETs) or other nonvolatile devices to perform in-memory operations
Implementation Method 2
During a charging phase, the capacitor accumulates charge based on the conduction state of the transistor and an input voltage applied to the bit line
Implementation Method 3
During a compute phase, the sense node exchanges charge with one or more other sense nodes in the array, such that a resulting voltage reflects an analog output of a multiply-accumulate (MAC) operation
Data Source
AI summary
A CiM architecture is disclosed, including memory cells each having a nonvolatile memory transistor and a capacitor connected in series between a bit line and a sense node. The transistor is configured to store a programmable state corresponding to a weight value and to selectively conduct based on a control voltage applied to a gate terminal. During a charging phase, the capacitor accumulates charge based on the conduction state of the transistor and an input voltage applied to the bit line. During a compute phase, the sense node exchanges charge with one or more other sense nodes in the array, such that a resulting voltage reflects an analog output of a MAC operation. The disclosed architecture can support binary and/or multi-bit computation and, in some cases, can utilize FeFETs or other nonvolatile devices to perform in-memory operations with improved variation resilience and energy efficiency.