Memory Command Sampling Circuit for 1N Timing Windows
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Solution Overview
Problem
Existing DRAM technologies face inefficiencies in command sampling due to transmission delays and missed data windows, particularly in high-frequency operations, leading to failures in the 1N mode.
Innovation Solution
A command sampling circuit that includes a sampling circuit and a delay circuit, which samples memory commands at multiple edges of a sampling clock, with a delay circuit to ensure timely decoding and address information output, reducing the need for multiple flip-flop stages and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple flip-flop stages are used to sample commands at multiple clock edges, then command sampling accuracy is improved, but transmission delay increases and data windows may be missed
Solution Approach 1:
The command sampling circuit is divided into two independent sampling paths: a first sampling path that samples the first cycle command at a first clock edge, and a second sampling path that samples the second cycle command at a second clock edge. Each path operates independently with its own flip-flop stage, allowing simultaneous sampling without cascading delays. This segmentation eliminates the cumulative transmission delay that would occur with sequential multi-stage flip-flop sampling while maintaining accurate sampling at multiple clock edges.
2Reliability
If multiple flip-flop stages are used to ensure proper timing, then sampling reliability is improved, but circuit complexity increases
Solution Approach 1:
The circuit is segmented into parallel sampling paths rather than using sequential multi-stage flip-flops. Each path contains a single flip-flop that samples its respective command at the appropriate clock edge. This parallel segmentation achieves the same reliability goal as multi-stage sampling but with fewer total flip-flop stages and reduced circuit complexity.
Solution Approach 2:
The sampling circuit is designed to handle both 1N mode (single clock edge sampling) and 2N mode (dual clock edge sampling) operations through a unified architecture. The same sampling circuit structure and timing mechanism work for both modes, eliminating the need for separate circuit paths or additional control logic that would increase complexity.
3Measurement precision
If commands are sampled sequentially through multiple cycles, then sampling accuracy is improved, but productivity decreases due to longer processing time
Solution Approach 1:
The command sampling is segmented into parallel paths that simultaneously process different command cycles. The first sampling path and second sampling path operate concurrently, each capturing their respective commands at the appropriate clock edges. This parallel processing eliminates the sequential time consumption while maintaining the accuracy of multi-cycle sampling.
Solution Approach 2:
The circuit maintains continuous operation by sampling commands at multiple clock edges within the same operational cycle rather than requiring separate cycles for each sampling operation. The first and second sampling paths continuously capture commands as they arrive, eliminating idle time and maintaining productive throughput while ensuring accurate sampling.
Data Source
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AI summary
The present disclosure provides a command sampling circuit and a memory. The command sampling circuit includes a sampling circuit and a delay circuit. The sampling circuit receives a memory command and a sampling clock, samples the memory command separately in response to a first sampling edge and a second sampling edge of the sampling clock, and outputs a first cycle command and a second cycle command; the sampling circuit has a first output end and a second output end; the delay circuit delays a command output at the first output end of the sampling circuit and then outputs a delayed command; a command decoding circuit receives an output clock, decodes the commands output by the sampling circuit, and outputs, in response to an output edge of the output clock, a current decoded result as decoding information of the memory command; an address output circuit receives the output clock and outputs, in response to the output edge, a command currently output at the second output end of the sampling circuit as address information of the memory command. This solution can improve the efficiency of command sampling.