Shared Match Lines in Content Addressable Memory Arrays

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Solution Overview

Problem

Content addressable memory (CAM) arrays face challenges in power dissipation and search speed due to the need for extensive comparison circuitry and high dynamic power consumption, particularly in NOR-type architectures, which trade off speed for increased power usage, while NAND-type architectures are slower and less power-efficient.

Innovation Solution

The implementation of shared match lines in CAM arrays, where each row is divided into groups with sub-match lines and a super-match line, reducing the number of transistors required for match signaling, thereby minimizing power consumption and enhancing search speed without compromising performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If NOR-type CAM architecture is used, then search speed is improved, but power consumption increases

Engineering Contradiction:

Improvesearch speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides each row of CAM cells into multiple groups, with each group having its own sub-match line. Multiple sub-match lines are then combined through a super-match line to produce the final row match signal. This segmentation allows only the sub-match lines corresponding to matching groups to be charged, significantly reducing the number of transistors that need to be charged compared to traditional NOR architecture where all match lines are charged regardless of matches.

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If NAND-type CAM architecture is used, then power consumption is reduced, but search speed decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidsearch speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent segments the match line charging process into two stages: first, sub-match lines are charged in parallel through segmented groups of CAM cells; second, the super-match line is charged only if all sub-match lines indicate matches. This segmented approach maintains the parallelism needed for fast search while reducing the total number of transistors charged, achieving both speed and power efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary matching by charging sub-match lines for each group before combining them through the super-match line. This preliminary action allows early termination of the charging process for rows that have mismatches in any group, preventing unnecessary charging of the full match line and thus reducing power consumption while maintaining fast search speed.

Inventive Principle:

Principle #10Preliminary action

3Device complexity

If traditional CAM architecture with individual match lines is used, then match signaling is simple, but the number of transistors increases

Engineering Contradiction:

Improvenumber of transistorsVSAvoidmatch signaling simplicity

Core Design Contradiction:

Device complexityVSEase of operation

Solution Approach 1:

The patent merges multiple sub-match lines from different groups into a single super-match line using a combination logic circuit. This merging reduces the total number of match lines needed in the system while maintaining the ability to detect matches across all groups. The super-match line is charged only when all sub-match lines indicate matches, providing a compact representation of the match status.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7408797B2Methods and apparatus for content addressable memory arrays including shared match lines

Publication Date: 2008.08.05 INTEL CORP

AI summary

Embodiments of the present invention provide content addressable memory (CAM) arrays that include shared match lines. Other embodiments may be described and claimed.