DRAM Mode Register Updates for Faster Memory Training
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Solution Overview
Problem
Existing memory controller training methods for DRAM devices are slow and inefficient due to the use of sideband buses, which operate at low speeds, and the limited flexibility of MPC commands, leading to significant delays and an increasing need for MPC opcodes that are not scalable.
Innovation Solution
Implementing an MRUPD mode for in-band register updates, allowing direct configuration of DRAM and RCD registers without relying on sideband buses, thereby accelerating training and reducing the need for MPC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sideband bus is used for DRAM configuration and training, then configuration can be performed before CA bus training, but training speed becomes significantly delayed due to low sideband bus speed
Solution Approach 1:
The patent merges the configuration function into the CA bus transaction itself, eliminating the need for separate sideband bus transactions. The DRAM device performs configuration updates as part of the normal CA bus operation, combining what were previously separate processes into a single integrated flow, thereby achieving both reliable configuration and fast training speed.
2Device complexity
If MPC commands are used for DRAM training, then training can be performed with limited mode registers, but the number of required MPC opcodes increases and scalability is reduced
Solution Approach 1:
The patent introduces a dynamic mode register update mechanism where the DRAM device can be configured in different modes (MRUPD mode and traditional MRW mode) based on the training requirements. This dynamic approach allows the system to adapt to various training scenarios without requiring a fixed set of MPC opcodes, thereby improving scalability and reducing the number of required commands.
3Reliability
If traditional MRW mode is used for mode register updates, then CA bus must be trained first, but this creates a dependency that delays configuration programming
Solution Approach 1:
The patent enables preliminary configuration of DRAM mode registers before the CA bus is fully trained by using the sideband bus to load configuration data into the DRAM device. Once configured, the DRAM can perform self-configuration updates during normal operation, eliminating the need to wait for CA bus training completion before programming configuration, thus reducing configuration delay while maintaining command transmission reliability.
Data Source
AI summary
A configuration register update mode can be implemented as an MRUPD (mode register update) mode for a DRAM (dynamic random access memory) device. In one example, the MRUPD can also be applied to update an RCD (registering clock driver). In the update mode, the memory device (either the RCD or the DRAM) can perform configuration of any number of configuration registers with in-band register writes. The in-band register writes can be used to configure DFE (decision feedback equalization) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.