Word-Line Voltage Boosting via Parasitic Capacitance
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Solution Overview
Problem
As electronic devices transition to smaller scale technology nodes, the limited standard power supply voltages (e.g., 5V, 3V, 1.8V, 0.9V) restrict the minimum supply voltage for word-line operation in memory devices, leading to write failures and read disturb failures, and existing solutions require additional circuitry or separate power sources for voltage boosting.
Innovation Solution
The method involves using parasitic capacitances between the word-line and a dummy line, leveraging PMOS transistors to boost the word-line voltage by controlling the resistance and duration of switch closures, without requiring additional circuit elements or power sources, and pre-discharging the dummy line to ground potential before operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If standard power supply voltages are used in smaller scale technology nodes, then device scaling is achieved, but word-line voltage becomes insufficient leading to write failures and read disturb failures
Solution Approach 1:
The patent changes the voltage parameter dynamically by coupling a dummy line to the supply voltage to boost the word-line voltage above the standard supply voltage level, thereby maintaining reliable write operations despite scaling to smaller technology nodes with lower standard voltages
Solution Approach 2:
The patent introduces a dummy line as an intermediary element that couples between the supply voltage and the word-line through parasitic capacitance, enabling voltage boosting without requiring additional power sources or complex circuitry
2Reliability
If power supply voltage is boosted to improve write operations, then write margin is improved, but additional circuitry and power sources are required
Solution Approach 1:
The patent employs self-service by utilizing the inherent parasitic capacitance between the dummy line and word-line, along with the body effect of PMOS transistors, to achieve voltage boosting without external power sources or additional active circuit elements
Solution Approach 2:
The patent extracts and utilizes the parasitic capacitance that naturally exists in the CMOS process between the dummy line and word-line, converting what is typically considered a parasitic effect into a useful mechanism for voltage boosting
3Reliability
If voltage boosting circuitry is added to overcome voltage limitations, then word-line voltage is sufficient, but chip area increases
Solution Approach 1:
The dummy line serves multiple functions: it acts as a voltage boosting mechanism through parasitic capacitance coupling, provides shielding for the word-line, and can be integrated into existing memory cell structures without requiring dedicated voltage boosting circuitry
Solution Approach 2:
The patent merges the voltage boosting function with the existing dummy line structure that is already present in many memory designs for shielding or other purposes, thereby achieving voltage boosting without adding separate dedicated circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory performance by boosting the word-line voltage above the supply voltage, reducing chip area and power management complexity, and improving write margin without slowing down memory operations, thus addressing the limitations of existing solutions.
Implementation Method 1
techniques to boost word-line voltage using parasitic capacitances
Implementation Method 2
leveraging a low-to-high voltage transition of gate-drain parasitic capacitances of the PMOS transistors to further boost the word-line voltage
Data Source
Figure 1A
Figure 1B~1C
Figure 2
AI summary
A memory device with word-line voltage boosting includes a set of first switches that are operable to couple a word-line of the memory device to a supply voltage to pull the word-line up to a rail voltage. A dummy line including a conductive route can be disposed in a vicinity of the word-line to form a parasitic coupling capacitance with the word-line. A second switch is operable to couple the dummy line to the supply voltage to pull the dummy line to the rail voltage. Pulling up the dummy line boosts the word-line voltage above the rail voltage by a boost voltage.