Signal Line Biasing Circuit for Memory Array Preemphasis Control
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Solution Overview
Problem
In memory systems, signal lines are prone to propagation delays due to their length, leading to unacceptable delays in memory operations, especially at increasing operating frequencies, and existing methods for biasing signals lack control over preemphasis magnitude and duration, resulting in wasted power and suboptimal performance.
Innovation Solution
The implementation of a microcontroller that dynamically controls the biasing signals for signal lines by determining the duration, magnitude, and shape of preemphasis, using signal line drivers with digital to analog converters and current sources, to efficiently and quickly achieve target voltage conditions along the signal lines, considering operating conditions such as temperature and power constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If signal lines are made longer to increase storage density, then storage capacity is improved, but propagation delay increases
Solution Approach 1:
The patent applies preliminary action by pre-emphasizing the biasing signal before it is applied to the signal line. The biasing signal is boosted to a higher magnitude for a predetermined duration before the actual memory operation, which accelerates the propagation of the signal along the extended signal lines and reduces the delay in reaching distant memory cells.
Solution Approach 2:
The patent implements dynamics by making the biasing signal magnitude time-dependent. The signal line driver dynamically adjusts the biasing signal magnitude according to a predetermined waveform that provides higher magnitude initially and then reduces it, allowing the system to adapt to the propagation characteristics of long signal lines and minimize delay.
2Loss of time
If preemphasis is applied to speed up signal propagation, then propagation delay is reduced, but power consumption increases
Solution Approach 1:
The patent applies periodic action by using a time-varying preemphasis waveform that is applied only during a predetermined period before the memory operation. The biasing signal magnitude follows a predetermined waveform that provides enhanced magnitude initially and then reduces, allowing the system to benefit from accelerated propagation only when needed, thereby reducing overall power consumption compared to continuous high-magnitude signaling.
Solution Approach 2:
The patent implements parameter changes by dynamically varying the magnitude of the biasing signal according to a predetermined waveform. The signal line driver changes the signal parameters (magnitude over time) to optimize propagation speed during the critical initial period, then reduces the magnitude to minimize power consumption during subsequent periods when the signal has already propagated.
3Quantity of substance
If signal lines are placed closer together to increase density, then storage capacity is improved, but signal interference increases
Solution Approach 1:
The patent applies preliminary action by pre-biasing the signal lines before memory operations occur. This preliminary biasing establishes a stable voltage baseline on closely spaced signal lines, reducing susceptibility to interference from adjacent lines during subsequent read/write operations and enabling higher density configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces propagation delays, optimizes power usage, and enhances memory operation efficiency by adaptively managing the preemphasis of biasing signals, ensuring timely and effective memory operations across varying conditions.
Implementation Method 1
signal line drivers with digital to analog converters
Implementation Method 2
current sources, to efficiently and quickly achieve target voltage conditions along the signal lines
Data Source
AI summary
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.