Write-Assist Memory Circuit for Lower-Voltage Resistive Writes

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Solution Overview

Problem

Non-volatile memory devices using variable resistance require high voltages for write operations, which affect the reliability and energy consumption of the memory cells and peripheral circuits.

Innovation Solution

A memory device with a write assist unit that controls voltages applied to the memory array, using a current limit circuit and transistors to reduce voltages during write operations, improving energy efficiency and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high voltage is applied to change resistance state of memory element, then write operation is enabled, but energy consumption increases and reliability decreases

Engineering Contradiction:
Improvememory cell reliabilityVSAvoidwrite operation energy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The write operation is divided into multiple phases with different voltage levels. A first voltage is applied to bit lines while a second voltage is applied to source lines, allowing the write current to be distributed and controlled through separate line pairs, thereby reducing peak current stress on individual memory cells and improving reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dummy memory cells are introduced as intermediary elements between the write assist unit and the actual memory cells. These dummy cells absorb excess write current and prevent direct high-current stress on functional memory cells, reducing degradation and improving reliability without compromising write capability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If high voltage is applied to change resistance state of memory element, then write operation is enabled, but device complexity increases

Engineering Contradiction:
Improvememory device reliabilityVSAvoidwrite assist circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The write assist unit performs multiple functions: it generates controlled voltage levels for bit lines and source lines, manages write current distribution, and protects memory cells from excessive current. This multi-functional design consolidates what could be multiple separate circuits into a single integrated unit, reducing overall device complexity while maintaining reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The write assist unit dynamically adjusts voltage parameters (first voltage level, second voltage level) based on operational requirements. By changing voltage parameters rather than using fixed high voltage, the system achieves reliable writes with reduced stress on memory cells, avoiding the need for more complex protection circuits

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The reduced voltages improve the energy consumption and reliability of the memory device by mitigating the impact of high write currents on memory cells and peripheral circuits.

Implementation Method 1

A type of non-volatile memory device using variable resistance has been developed, with each memory cell containing a memory element that can alter its resistance. This element can switch between high and low resistance states in response to electrical signals

Methodology Applied
Scientific EffectVariable resistance: Electrical Resistance

Implementation Method 2

a write assist unit that generates a first voltage to a current limit circuit and controls, in response to a control signal, a second voltage coupled between the current limit circuit and the memory array

Methodology Applied
Scientific EffectVoltage generation: Electric Field

Data Source

PatentUS20260045299A1Memory device and operating method thereof
Publication Date: 2026.02.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260045299A1 patent drawing
  • US20260045299A1 patent drawing
  • US20260045299A1 patent drawing

AI summary

A memory device is provided, including a memory array; a current limit circuit coupled to the memory array; and a write assist unit that generates a first voltage to the current limit circuit and controls, in response to a control signal, a second voltage coupled between the current limit circuit and the memory array. The current limit circuit transmits at least one write current flowing through the memory array in response to the first voltage and the second voltage.