Magnetic Resistor Bit-Cell Array for Neuromorphic Computing
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Solution Overview
Problem
Existing magnetic tunnel junction (MTJ) elements used in neural network hardware can only store binary resistance values, making it difficult to store various resistance values and have slow write operation speeds, limiting their ability in neuromorphic processing.
Innovation Solution
A processing apparatus with a bit-cell array that includes first and second magnetic resistors, each storing different resistance values based on magnetic domain-wall movement, and switching elements to control electrical signals, enabling multiplication and addition computations without complex logic gates, and performing computations quickly and efficiently at low power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an existing MTJ element is used to store resistance values, then the structure is simple, but only binary resistance values can be stored and write operation speed is slow
Solution Approach 1:
The MTJ element is segmented into multiple magnetic resistors (first magnetic resistor, second magnetic resistor, etc.) connected in series, where each magnetic resistor can independently store different resistance values. This segmentation allows the system to store multiple analog resistance values rather than just binary values, while maintaining relatively simple individual component structures.
Solution Approach 2:
The patent introduces dynamic control through switching elements (first switching element, second switching element) that can selectively connect different magnetic resistors to the circuit. This dynamic switching capability enables fast reconfiguration of the resistance values without requiring physical movement or complex writing operations, thereby improving write operation speed.
2Adaptability or versatility
If an existing MTJ element is used, then the device complexity is low, but the capability to store various resistance values is limited
Solution Approach 1:
The bit-cell is segmented into multiple magnetic resistors connected in series, with each resistor capable of storing different resistance values. This segmentation multiplies the total number of storable resistance values while keeping each individual magnetic resistor relatively simple in structure.
Solution Approach 2:
The switching elements serve multiple functions: they control the selection of different magnetic resistors, enable fast reconfiguration of resistance values, and maintain compatibility with existing MTJ element structures. This multi-functionality increases adaptability without proportionally increasing device complexity.
3Productivity
If complex logic gates are used to perform multiplication and addition computations, then computation accuracy is high, but power consumption increases and computation speed decreases
Solution Approach 1:
The patent replaces complex electronic logic gate systems with a simplified system based on magnetic resistors and switching elements. The multiplication and addition computations are performed through the inherent electrical characteristics of the magnetic resistors (Ohm's law) rather than through complex logical operations, thereby reducing power consumption and increasing computation speed.
Solution Approach 2:
The patent extracts the computation function from the traditional logic gate-based processing unit and implements it directly in the memory structure using magnetic resistors. This extraction eliminates the need for complex logic gates while maintaining computation capability, resulting in lower power consumption and faster operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The apparatus can store various resistance values and perform computations efficiently and quickly, enhancing neuromorphic processing capabilities beyond traditional MTJ limitations.
Implementation Method 1
a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall
Data Source
AI summary
A processing apparatus includes a bit-cell array including at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series, wherein each of the plurality of bit-cells includes: a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall; a second magnetic resistor that is configured to store a second resistance value, wherein the second resistance value is equal to or less than the first resistance value; a first switching element configured to switch an electrical signal applied to the first magnetic resistor; and a second switching element configured to switch an electrical signal applied to the second magnetic resistor.