Four-Gate Non-Volatile Memory Synapses for Energy-Efficient Neural Networks
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Solution Overview
Problem
Current artificial neural networks face challenges in high-performance information processing due to inadequate hardware technology, specifically high energy inefficiency and bulky CMOS-implemented synapses, which hinder the development of efficient and scalable neural networks.
Innovation Solution
The development of a neural network device utilizing a combination of CMOS technology and non-volatile memory arrays, where memory cells with floating gates and multiple gates are arranged in rows and columns to enable precise and efficient storage and tuning of synapse weights, allowing for individual programming, erasure, and reading of memory cells without affecting others, and enabling continuous analog programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS analog circuits are used for artificial neural networks, then the neural network can be implemented with standard semiconductor technology, but the synapses become too bulky given the high number of neurons and synapses required
Solution Approach 1:
The patent replaces traditional CMOS transistor-based synapse implementations with non-volatile memory cells (such as flash memory or resistive memory) to store synapse weights. This substitution reduces the area required per synapse while maintaining the ability to programmably set weight values, directly addressing the bulkiness problem of CMOS-based synapses in large-scale neural networks
Solution Approach 2:
The patent changes the fundamental parameter of how synapse weights are stored and accessed by using non-volatile memory technology instead of volatile CMOS circuits. This parameter change enables smaller synapse footprints while preserving the programmable weight adjustment capability essential for neural network operation
2Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then the neural network can achieve high computational parallelism, but the energy efficiency deteriorates as compared to biological networks
Solution Approach 1:
The patent employs non-volatile memory cells that retain their weight values without requiring continuous power supply, enabling the neural network to maintain its computational state with minimal energy consumption. The memory cells themselves perform the weight storage function without needing separate volatile memory components, reducing overall system energy requirements while maintaining high computational parallelism
Solution Approach 2:
The patent substitutes traditional volatile memory and processing architectures with non-volatile memory-based synapses that inherently provide both storage and computation capabilities, reducing the energy overhead associated with maintaining computational states in digital supercomputers and GPU clusters
3Productivity
If a large number of synapses are implemented to enable high connectivity between neurons, then the computational parallelism increases, but the device complexity and cost increase
Solution Approach 1:
The patent merges the synapse weight storage function directly into the memory cell structure, eliminating the need for separate volatile memory components and control logic that would be required in traditional CMOS implementations. This merging simplifies the overall hardware architecture while enabling large numbers of synapses to be implemented with reduced complexity and cost
Solution Approach 2:
The patent uses universal non-volatile memory cell structures that can serve multiple functions: storing synapse weights, retaining values without power, and being programmably adjusted. This multi-functionality reduces the need for specialized components, thereby reducing device complexity and cost while supporting high computational parallelism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the energy efficiency and scalability of neural networks by allowing precise tuning of synapse weights, reducing the complexity and cost of hardware, and enabling efficient processing with minimal disturbance to other memory cells, thus improving the overall performance of neural network operations.
Implementation Method 1
Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
a first gate disposed over and insulated from a second portion of the channel region, a second gate disposed over and insulated from the floating gate
Data Source
Figure 1~2
Figure 3
Figure 4~6
AI summary
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.