3D Memory Array Structure for Dense Stable Non-Volatile Cells
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Solution Overview
Problem
Existing semiconductor memory technologies, such as SRAM and DRAM, lose stored data when powered off due to their volatile nature, while non-volatile options like FeRAM offer fast write/read speeds but may face challenges in achieving high memory cell density and structural stability during manufacturing.
Innovation Solution
A three-dimensional memory array is fabricated using a multilayer stack of alternating dielectric layers, with conductive features and ferroelectric strips for data storage, allowing for high aspect ratios and precise patterning to enhance memory cell density and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional volatile memory structures (SRAM/DRAM) are used, then manufacturing is simpler, but data is lost when powered off
Solution Approach 1:
The patent transitions from planar 2D memory structures to three-dimensional vertical structures. Memory cells are stacked in multiple layers with word lines extending vertically, enabling non-volatile storage while maintaining manufacturing feasibility through standardized layer-by-layer fabrication processes
Solution Approach 2:
The invention employs composite material structures combining conductive materials (for electrodes and interconnects), dielectric materials (for isolation and capacitance), and ferroelectric materials (for non-volatile data storage). This composite approach achieves data retention without sacrificing manufacturing compatibility
2Quantity of substance
If FeRAM structures are used, then write/read speed is fast, but memory cell density and structural stability are compromised
Solution Approach 1:
By stacking memory cells vertically across multiple layers, the patent achieves high memory cell density without compromising structural stability. The vertical arrangement allows tighter packing while maintaining mechanical integrity through supported scaffolding structures
Solution Approach 2:
The memory array is divided into multiple stacked layers, each containing complete memory cell structures. This segmentation enables independent fabrication and alignment of each layer, improving both density and structural stability through modular construction
3Quantity of substance
If high aspect ratio structures are used, then memory cell density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses vertical stacking to achieve high density while maintaining manageable aspect ratios through controlled layer thicknesses. Each layer is fabricated with standard precision requirements, and the cumulative vertical arrangement achieves the overall high density target
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a non-volatile memory array with improved memory cell density and structural stability, facilitating efficient data storage and retrieval with reduced defects and twisting or collapsing issues.
Implementation Method 1
a ferroelectric strip adjacent a second side of the first charge trapping strip
Data Source
AI summary
3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.