SRAM Leakage Reduction via Virtual Ground Segmentation
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Solution Overview
Problem
SRAM memory circuits face challenges in minimizing leakage currents, particularly at low supply voltages, which affects the I ON / I OFF ratio and power consumption, especially in IoT applications where 'normally OFF / instant ON' modes are used, and existing solutions either reduce the number of memory cells per column or introduce complex booster circuits that increase static and dynamic consumption.
Innovation Solution
The proposed SRAM memory design incorporates local and global virtual ground lines coupled with control elements that include PMOS and NMOS transistors, allowing for zero potential difference between bit lines and read ports in standby mode, thereby eliminating leakage currents without reducing the number of memory cells per column or increasing surface area, and using a general control element with an inverter configuration to manage the virtual ground potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional access transistors and/or read ports are added to an SRAM cell, then the memory circuit can perform simultaneous read and write operations, but the I OFF leakage currents of the cell increase
Solution Approach 1:
The patent divides the virtual ground control into two independent parts: local virtual ground lines (LVGND) controlled by local control elements for each memory cell line, and a global virtual ground line (GVGND) controlled by a general control element. This segmentation allows selective activation of control elements based on whether the memory operates in single-port or dual-port mode, thereby reducing leakage currents in unused read ports while maintaining functionality when needed.
2Loss of energy
If the number of memory cells per column is reduced to limit leakage current, then the overall leakage current is reduced, but the number of columns decreases which may require additional local inputs/outputs
Solution Approach 1:
The patent implements dynamic control of the virtual ground potential through control elements that can switch between different states. The local control elements can be activated or deactivated based on the operational mode (single-port or dual-port), allowing the system to adapt its leakage characteristics dynamically without changing the physical layout or number of memory cells per column.
3Ease of operation
If a virtual ground line is connected to ground for reading memory cells, then leakage currents are enabled for reading, but leakage currents are generated in the control elements when not in use
Solution Approach 1:
The patent extracts the virtual ground function from a fixed ground connection and implements it through controllable virtual ground lines that can be selectively connected to ground or to the supply potential. This allows the system to take out the leakage current path when reading is not needed, while maintaining reading capability when required.
Solution Approach 2:
The patent changes the electrical potential parameter of the virtual ground lines dynamically. The local control elements can switch the potential of LVGND lines between the supply potential (for low leakage in standby mode) and ground (for reading operation). This parameter change allows the system to optimize leakage currents based on operational state.
Data Source
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AI summary
SRAM memory (100) comprising: - a memory cell matrix (102); - bit lines (110) and word lines (112); - read ports (104) associated with the memory cells and coupled to the bit lines and word lines; - local virtual ground lines (122), LVGND, each coupled to reference potential terminals of the read ports of at least one memory cell line; - local control elements (124) each configured to electrically couple one of the LVGND lines to a supply potential or to a general virtual ground line (130), or GVGND line; - a general control element (132) configured to couple the GVGND line to the electrical supply potential or to an electrical reference potential.