In-Memory Spiking Neural Unit for Threshold Weight Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory technologies, such as volatile and non-volatile memory devices, face challenges in efficiently processing and storing data for applications like artificial neural networks, particularly in terms of processing time and performance.
Innovation Solution
Integration of spiking neural units within complementary metal-oxide-semiconductor (CMOS) structures that include logic for increasing, collecting, and comparing weights in memory cells, with multiplexors and comparators to determine learning events and output results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing memory technologies are used for data processing in neural networks, then data storage capability is maintained, but processing time increases and performance decreases
Solution Approach 1:
The patent combines memory cells with spiking neural unit logic circuits into an integrated structure where memory and processing functions coexist. The logic circuit is directly coupled to the memory cell array, enabling simultaneous storage and computation operations without data transfer delays between separate components.
Solution Approach 2:
The memory device is designed to perform multiple functions: it serves as both a storage medium for weights and as a processing unit for neural network computations. The same memory infrastructure supports both data retention and active computation through the integrated spiking neural units.
2Productivity
If traditional memory architectures are used, then structural simplicity is maintained, but processing efficiency decreases
Solution Approach 1:
The spiking neural unit is divided into distinct functional components: weight storage elements, logic circuitry for spike generation, and comparison units for threshold evaluation. This segmentation allows each component to be optimized independently while working together as an integrated processing unit.
Solution Approach 2:
The patent transitions from traditional von Neumann architecture to a more integrated memory-compute architecture by adding the dimension of spatial co-location. Processing elements are positioned directly at the memory location, creating a three-dimensional functional integration that reduces data movement paths.
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS includes a spiking neural unit comprising logic configured to receive an input to increase a weight stored in a memory cell of the memory array, collect the weight from the memory cell of the memory array, accumulate the weight with an increase based on the input, compare the accumulated weight to a threshold weight, and provide an output in response to the accumulated weight being greater than the threshold weight.