Word Line Driver Circuit Leakage Reduction
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Solution Overview
Problem
Conventional word line drivers in memory devices suffer from high leakage current, particularly due to the large number of driver circuits required for moderate-sized memory arrays, which increases power consumption and access time, and existing solutions like stacked PMOS devices are inefficient in reducing leakage current effectively.
Innovation Solution
A word line driver circuit that groups multiple rows of drivers into a single driver and employs a switching circuit with transmission gates and switch devices to selectively connect word lines to a prescribed voltage, reducing leakage current by eliminating current paths when drivers are not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple word line drivers are employed to drive each word line, then the word line can be driven to achieve reasonable memory access times, but the leakage current increases significantly
Solution Approach 1:
The patent combines multiple word line drivers (specifically 4 drivers) into a single integrated driver circuit. This single driver uses transmission gates and control logic to selectively connect to different word lines (WL0-WL3) based on decode signals, thereby reducing the total number of independent driver circuits while maintaining the ability to drive multiple word lines at different times
2Loss of energy
If the number of driver circuits is reduced to lower leakage current, then power consumption decreases, but the ability to drive large word line loads is compromised
Solution Approach 1:
The patent implements dynamic switching within the single driver circuit using transmission gates controlled by decode signals. The driver can dynamically connect to different word lines based on which row is being accessed, allowing one driver to perform the work of multiple drivers at different times. This dynamic allocation maintains driving capability while reducing static leakage
3Loss of energy
If conventional stacked PMOS devices are used to reduce leakage, then some leakage reduction is achieved, but the intermediate node takes significant time to equalize to low-current state
Solution Approach 1:
The patent extracts the word lines from a permanently active state and places them in a high-impedance disconnected state when not in use. The transmission gates act as switches that completely isolate inactive word lines from the driver output, rather than relying on slow leakage-based equalization. This extraction of inactive word lines from the active circuit eliminates the equalization time problem
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage current by up to 75% while maintaining performance, as the number of drivers is reduced, and the use of complementary transmission gates minimizes leakage during inactive states, allowing for efficient power management in memory devices.
Implementation Method 1
a switching circuit (201) connected to the output node (N2) of the driver and operative to selectively connect a selected one of the plurality of word lines (WL[3:0]) to a prescribed voltage level in response to a control signal
Data Source
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AI summary
A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.