Semiconductor Memory Clock Control for Wafer Testing
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Solution Overview
Problem
High-speed semiconductor memory apparatuses face challenges in wafer-level testing due to inadequate evaluation of target frequency characteristics, leading to increased manufacturing costs and reduced yield, as conventional test equipment often cannot input high enough frequencies to properly assess chip performance before packaging.
Innovation Solution
A semiconductor memory apparatus with a clock control unit that generates a second clock with a cycle closer to the target frequency, allowing for internal DLL and AC circuit operation at high speeds, enabling effective evaluation of target frequency characteristics using existing outmoded test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test equipment is used to test semiconductor memory apparatus at wafer level, then testing cost is reduced and manufacturing process is simplified, but the maximum frequency value of input clock signal falls short of target frequency, causing inadequate testing of high-speed operation characteristics
Solution Approach 1:
A clock control unit is introduced as an intermediary component between the conventional test equipment and the semiconductor memory apparatus. This unit receives a first clock signal from the test equipment and generates a second clock signal with frequency closer to the target frequency, enabling accurate high-speed operation testing while继续使用 conventional low-cost test equipment
Solution Approach 2:
The clock control unit changes the frequency parameter of the clock signal by receiving a first clock signal at a lower frequency and generating a second clock signal at a higher frequency closer to the target frequency. This parameter transformation enables the semiconductor memory apparatus to be tested at its intended operating frequency without requiring expensive high-frequency test equipment
2Reliability
If semiconductor memory apparatus is tested at target frequency using advanced test equipment, then high-speed operation characteristics can be properly evaluated, but manufacturing period and manufacturing cost increase
Solution Approach 1:
The clock control unit serves as a mediator that bridges the gap between conventional test equipment capabilities and the high-speed testing requirements. By generating the appropriate high-frequency clock signal internally, it enables reliable quality assessment without requiring external advanced test equipment, thus avoiding increased manufacturing time and cost
3Ease of manufacture
If wafer level testing is performed with existing equipment, then manufacturing cost is reduced, but defective chips cannot be filtered in advance, leading to decreased packaging yield and increased rework
Solution Approach 1:
The clock control unit enables preliminary action by allowing high-frequency operation characteristic testing to be performed at the wafer level before packaging. This advance testing identifies defective chips early in the manufacturing process, enabling their filtering before packaging occurs, thus preventing waste of packaging resources and improving overall manufacturing efficiency
Data Source
AI summary
A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.