Configurable Memory Metadata Layout for Host-Managed ECC
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Solution Overview
Problem
Existing error correction schemes in computing devices are inefficient and costly, particularly due to the use of high-density on-chip SRAM for system-level ECC, which increases system cost and susceptibility to soft errors.
Innovation Solution
Implementing a system ECC function that shares signal connections with link ECC functions, eliminating the need for separate on-chip SRAM by generating system parity bits within the host and transferring them through existing data channels, thereby integrating ECC operations within the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density on-chip SRAM is used for system-level ECC, then error detection and correction capabilities are improved, but system cost increases and susceptibility to soft errors increases
Solution Approach 1:
The patent merges the system ECC function with the link ECC function by integrating both error correction operations within the memory array. Instead of using separate on-chip SRAM for system-level ECC, the patent combines multiple ECC operations to share resources and reduce overall system complexity and cost while maintaining comprehensive error detection and correction capabilities.
2Reliability
If separate on-chip SRAM is used for system ECC, then error protection is improved, but device complexity and susceptibility to soft errors increase
Solution Approach 1:
The patent combines system ECC and link ECC operations within the memory array to eliminate separate on-chip SRAM structures. This integration reduces the number of vulnerable memory components while maintaining comprehensive error protection through coordinated ECC operations across the unified memory structure.
Data Source
AI summary
Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.