Semiconductor Memory Device Data Writing Speed Optimization
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Solution Overview
Problem
Current semiconductor memory devices face limitations in operational speed during data writing operations, particularly in efficiently connecting and disconnecting data input and output lines to bit lines while minimizing contention with sense amplifiers.
Innovation Solution
The semiconductor memory device employs a method where column selection transistors are turned on during specific time intervals to connect data input and output lines to bit lines, while isolation transistors manage the connection and disconnection of bit lines from sense amplifiers, allowing for consecutive data writing operations without interfering with sense amplifier operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data input and output lines are connected to bit lines during writing operation, then data writing speed is improved, but contention with sense amplifier occurs reducing operational speed
Solution Approach 1:
The writing operation is divided into two sequential time intervals: first time interval for data writing (column selection transistors on, sense amplifier disconnected) and second time interval for sensing (isolation transistors on, sense amplifier connected). This temporal segmentation eliminates contention between writing driver and sense amplifier, resolving the contradiction between writing speed and operational reliability
Solution Approach 2:
Data is written to bit lines during the first time interval before the sense amplifier operation begins. This preliminary action ensures that data is ready on the bit lines before the sense amplifier connects in the second time interval, enabling seamless transition without contention and improving overall operational speed
2Reliability
If sense amplifier is connected to bit lines during data writing, then sensing capability is maintained, but writing operation is interfered with
Solution Approach 1:
The sense amplifier connection to bit lines is made periodic rather than continuous. It is disconnected during the first time interval (writing phase) and connected during the second time interval (sensing phase). This periodic action ensures sensing capability is maintained when needed while eliminating interference with writing operations
Solution Approach 2:
Isolation transistors are introduced as intermediary elements between the bit lines and sense amplifier. These transistors act as switches that control the connection timing, enabling the sense amplifier to be connected only during the second time interval when writing is complete, thus resolving the conflict between sensing capability and writing performance
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells connected a pair of bit lines, a column selection circuit, and a sense amplifier. When the semiconductor memory device is in a data writing operation, the column selection circuit electrically connects a pair of data input and output lines to the pair of bit lines during a first time interval and a second time interval, consecutively arranged, and the sense amplifier electrically disconnects from the pair of bit lines during the first time interval, and senses and amplifies a voltage difference between the pair of bit lines during the second time interval.