Hybrid Static Dynamic Memory Sensing Circuit
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Solution Overview
Problem
High-speed semiconductor memory sensing techniques face a trade-off between noise immunity and performance, as differential sense amplifiers are inefficient due to device variability, while dynamic NAND circuits improve speed but compromise noise immunity, and adding noise immunity measures like NFET keepers eliminate the speed advantage.
Innovation Solution
A hybrid circuit combining a skewed static logic gate with a dynamic pre-discharge device, allowing the static logic gate to operate as a dynamic circuit, achieving both high-speed sensing and improved noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dynamic NAND circuit is used for sensing, then sensing speed is improved, but noise immunity is compromised
Solution Approach 1:
The patent applies the dynamics principle by using a dynamic NAND circuit configuration where the bit line is pre-charged and then evaluated during the sensing operation. The dynamic nature of the circuit allows it to respond quickly to changes in bit line voltage, achieving fast sensing speeds while the specific dynamic logic design maintains adequate noise immunity through controlled voltage transitions and timing.
2Reliability
If NFET keeper is added to improve noise immunity, then reliability is improved, but speed advantage is eliminated
Solution Approach 1:
The patent extracts or removes the NFET keeper transistor from the sensing circuit. By eliminating this additional transistor, the circuit maintains its dynamic NAND structure without the extra component that would slow down the sensing operation. The removal of the keeper allows the circuit to achieve both fast sensing speeds and adequate noise immunity through the inherent properties of the dynamic NAND logic and proper timing control.
Solution Approach 2:
The patent employs a sensing approach that uses simple, transient voltage signals rather than requiring complex noise protection circuitry. The dynamic NAND circuit uses brief pre-charge and evaluate phases where voltage transitions are deliberately short-lived and disposable, allowing fast sensing without the need for NFET keepers that would extend signal duration and reduce speed.
3Reliability
If static NAND circuit is used for sensing, then noise immunity is improved, but sensing performance is poor
Solution Approach 1:
The patent transitions from a static NAND sensing circuit to a dynamic NAND sensing circuit. The dynamic configuration uses pre-charged bit lines and time-dependent evaluation, allowing the circuit to rapidly respond to sensing conditions. This dynamic approach maintains noise immunity through controlled voltage transitions and timing while dramatically improving sensing speed and overall performance compared to static circuits.
Data Source
AI summary
A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit.