DRAM Main I/O Line Hold Circuit for Lower Reset Power
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Solution Overview
Problem
Existing DRAM circuits face high power consumption and large power loss due to frequent row address switching in AI and mobile device applications, especially during multi-bit high-speed operations, as they require frequent resetting of main input/output lines after read and write cycles.
Innovation Solution
Implementing a latch circuit to hold the state of main input/output lines from the end of a write cycle to the start of the next read cycle, reducing the frequency of resetting and minimizing current consumption by maintaining the line state during consecutive write cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the main input/output line pair is precharged after every read and write cycle, then the reliability of data transfer is improved, but the power consumption increases due to frequent resetting operations
Solution Approach 1:
The patent applies periodic action by resetting the main input/output line pair only at specific intervals (after write cycles followed by read cycles) rather than after every single operation. The reset timing is controlled periodically based on the operation sequence, reducing unnecessary reset operations while maintaining data integrity.
Solution Approach 2:
The patent uses preliminary action by precharging the main input/output line pair in advance before read operations that require it, rather than resetting after every operation. The control circuit predicts when precharging is needed and performs it proactively, reducing the frequency of reset operations.
2Stability of the object's composition
If the main input/output line pair is reset after every write cycle, then the stability of the system state is improved, but the current consumption increases due to frequent precharging operations
Solution Approach 1:
The patent implements periodic action by resetting the main input/output line pair only periodically after specific operation sequences (write followed by read), rather than after every write cycle. This reduces the frequency of precharging operations while maintaining system stability when needed.
Solution Approach 2:
The control circuit automatically determines when resetting is necessary based on the operation sequence, making the system self-regulating. It monitors the state of the main input/output line pair and performs resetting only when required, eliminating unnecessary energy-consuming operations.
3Measurement precision
If frequent resetting of main input/output lines is performed, then the accuracy of signal levels is improved, but the heat generation increases due to high power loss
Solution Approach 1:
The patent applies periodic action by maintaining signal levels on the main input/output line pair for extended periods without resetting, only performing resets when necessary for signal accuracy. This reduces the frequency of precharging operations and consequently reduces heat generation from high-power switching events.
Solution Approach 2:
The patent changes the temporal parameter of signal maintenance, keeping the signal levels stable for longer durations rather than frequently resetting them. This parameter change reduces the frequency of high-power operations, thereby reducing heat generation while maintaining signal integrity.
4Stability of the object's composition
If the main input/output line pair is precharged after each operation, then the consistency of operation starting state is improved, but the productivity decreases due to increased power loss in multi-bit high-speed operations
Solution Approach 1:
The patent implements periodic action by resetting the main input/output line pair only at specific intervals rather than after every operation. This reduces the overhead of frequent precharging operations, improving the efficiency of multi-bit high-speed operations while maintaining consistent starting states when needed.
Solution Approach 2:
The patent maintains continuous operation of the main input/output line pair without frequent interruptions for resetting. By keeping the lines active and avoiding unnecessary precharging cycles, the system achieves continuous useful action, improving productivity in high-speed multi-bit operations.
Data Source
AI summary
A current consumption in a DRAM circuit is reduced. The DRAM circuit is a dynamic random access memory (DRAM) circuit provided with a main input/output line pair and a reset circuit. A potential of the main input/output line pair is held in a period from an end of a write cycle to a start of a first write cycle after the write cycle or a period from the end of the write cycle to a start of a first read cycle after the write cycle. The reset circuit resets a state of the main input/output line pair at a time of the start of the first read cycle.