Fast Sense Amplifier Bit-Line Pre-Charging
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Solution Overview
Problem
Conventional current sense amplifiers in emerging memory read operations require substantial stabilization time (>10 nanoseconds) and produce high spike currents, limiting high-speed read operations due to the need for current signals to settle from VDD to a reference level.
Innovation Solution
A memory cell with a pre-charged bit-line, utilizing pre-charge transistors to set the cell branch voltage to a predetermined level before read operations, reducing stabilization time by pre-charging the bit-line to a voltage close to the clamping voltage (VCL-Vthn), thereby shortening read times to less than 10 nanoseconds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional current sense amplifier is used with two-stage amplification, then reference current and cell current can be compared to generate logic output, but substantial stabilization time (>10 nanoseconds) is required for current signal to settle from VDD to reference level
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit-line to a voltage close to the clamping voltage (VCL-Vthn) before the read operation begins. This preliminary voltage setup reduces the stabilization time required for the current signal to settle, enabling faster read operations while maintaining measurement precision.
2Device complexity
If conventional current sense amplifier operates without pre-charging, then circuit design is simpler, but high spike currents are produced during read operations
Solution Approach 1:
The pre-charge transistor performs preliminary action by establishing the bit-line voltage before the read operation. This preliminary voltage preparation prevents sudden current transitions, thereby eliminating high spike currents while maintaining relatively simple circuit design.
3Productivity
If bit-line is pre-charged to voltage close to clamping voltage, then read time is reduced to less than 10 nanoseconds, but additional pre-charge transistor and control logic are required
Solution Approach 1:
The patent uses preliminary action through a pre-charge transistor that sets the bit-line voltage before the read operation. This approach achieves high read operation speed (less than 10 nanoseconds) by preparing the voltage state in advance, while the added circuit complexity is minimized through efficient use of the pre-charge transistor and its control logic.
Data Source
AI summary
A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.