Memory Bank Layout With Shared Data Lines for Higher Capacity
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Solution Overview
Problem
Existing memory technologies face challenges in achieving higher capacity and faster interaction speeds to accommodate increased data storage and processing demands in integrated systems.
Innovation Solution
A memory design with a specific layout that includes a first memory area, a peripheral circuit area, and a second memory area, where memory banks share global data lines and are split into tiles with optimized row and column decoders, and complementary regions to enhance capacity and reduce signal transmission errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased to accommodate higher data storage demands, then storage capacity improves, but signal transmission errors increase due to longer transmission distances
Solution Approach 1:
The memory array is divided into multiple memory banks, with each bank containing multiple tiles. This segmentation allows shorter transmission distances within each bank while achieving high overall capacity through parallel organization of multiple banks along the first direction.
Solution Approach 2:
Complementary regions are introduced as intermediary structures between memory banks. These complementary regions contain complementary decoders that generate complementary word line signals, acting as mediators to coordinate access across banks and reduce signal transmission errors in high-capacity configurations.
2Quantity of substance
If multiple memory banks are arranged to increase capacity, then storage capacity improves, but the number of global data lines increases complexity
Solution Approach 1:
Multiple memory banks share common global data lines through the peripheral circuit area. This merging approach allows banks to communicate through shared infrastructure rather than requiring dedicated lines for each bank, reducing overall complexity while maintaining high capacity.
Solution Approach 2:
Memory banks are arranged in the first direction (perpendicular to the second direction where tiles are arranged), creating a three-dimensional memory architecture. This dimensional organization allows capacity scaling without proportionally increasing data line complexity, as banks can share lines across the perpendicular dimension.
3Quantity of substance
If memory banks are arranged in the first direction perpendicular to the second direction, then memory capacity and organization improve, but manufacturing precision requirements increase
Solution Approach 1:
The memory is divided into standardized repeating units, each containing memory banks with standardized tile arrangements. This segmentation into modular units simplifies manufacturing by allowing repeated fabrication of identical blocks, reducing precision requirements compared to custom high-capacity designs.
Solution Approach 2:
Each memory bank and tile is designed with localized functionality and standardized dimensions. This local quality approach allows each unit to be manufactured independently with standard precision, while the overall high capacity emerges from the organized assembly of many such units in the first direction.
Data Source
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AI summary
Embodiments of this application provide a memory. The memory may include at least a first memory area, a peripheral circuit area, and a second memory area that are arranged in a first direction. The peripheral circuit area is located between the first memory area and the second memory area. The first memory area has a plurality of repeating units in a second direction. Each of the repeating units includes at least two memory banks arranged in the first direction. The first direction is perpendicular to the second direction.