DRAM Amplifier Circuit Dynamic Offset Cancellation
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Solution Overview
Problem
Dynamic random access memory (DRAM) amplifier circuits suffer from offset noise due to varying transistor features, leading to reduced effective readout margins and degraded performance, necessitating an efficient offset cancellation method that balances accuracy and processing time.
Innovation Solution
An amplifier circuit with a sensing amplification stage and an offset cancellation stage, where the duration of the offset cancellation stage is dynamically adjusted based on memory temperature using a processing circuit to optimize performance, reducing processing time while ensuring accurate offset cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If offset cancellation stage is performed to eliminate offset noise, then readout accuracy is improved, but processing time increases
Solution Approach 1:
The patent implements dynamic adjustment of the offset cancellation stage duration based on real-time temperature sensing. The control circuit modifies the time allocated for offset cancellation according to temperature conditions, making the processing time adaptive rather than fixed. This resolves the contradiction by optimizing the balance between accuracy and speed dynamically - longer cancellation time at temperatures where it's more beneficial, shorter time when speed is more critical.
Solution Approach 2:
The patent changes the operational parameter (duration of offset cancellation stage) based on temperature conditions. By sensing temperature and adjusting the cancellation time parameter accordingly, the system optimizes readout accuracy when temperature conditions warrant it while reducing processing time when speed is more important, thus resolving the trade-off between precision and time loss.
2Measurement precision
If offset cancellation stage duration is extended to improve cancellation accuracy, then offset noise reduction is improved, but data readout efficiency deteriorates
Solution Approach 1:
The system dynamically adjusts the offset cancellation duration based on temperature sensing rather than using a fixed extended duration. This allows the system to achieve sufficient cancellation accuracy only when temperature conditions require it, maintaining high data readout efficiency at other times. The dynamic adaptation resolves the contradiction between cancellation accuracy and readout efficiency.
Solution Approach 2:
The patent modifies the offset cancellation time parameter based on temperature conditions. By changing this parameter dynamically rather than extending it indefinitely, the system achieves the necessary cancellation accuracy while preserving overall data readout efficiency, thus resolving the contradiction between these two performance metrics.
3Loss of time
If temperature-based dynamic adjustment is implemented, then processing time optimization is improved, but device complexity increases
Solution Approach 1:
The patent segments the offset cancellation process into temperature-dependent stages by introducing a temperature sensing circuit and a control circuit that adjusts cancellation duration based on sensed temperature. This segmentation allows independent optimization of the cancellation process based on thermal conditions, achieving processing time optimization while containing complexity through modular addition of sensing and control functions.
Solution Approach 2:
The system implements feedback by sensing temperature and using this information to adjust the offset cancellation duration. The temperature sensor provides feedback about thermal conditions, and the control circuit uses this feedback to optimize processing time dynamically. This feedback mechanism achieves time optimization while managing complexity through a closed-loop control approach rather than complex open-loop timing circuits.
Data Source
AI summary
The present disclosure relates to an amplifier circuit, a control method, and a memory, including: a sensing amplification circuit, including a readout node, a complementary readout node, a first node, and a second node; an isolation circuit, coupled to the readout node, the complementary readout node, a bit line, and a complementary bit line, wherein the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line at a sensing amplification stage; an offset cancellation circuit, coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node, wherein the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node at an offset cancellation stage; and a processing circuit, coupled to the offset cancellation circuit.