Memory Array Leakage Reduction via Head and Foot Switches
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Solution Overview
Problem
As CMOS technology scales smaller, leakage current in memory arrays increases, posing a challenge for reducing power consumption in portable devices without sacrificing performance, as it affects battery life and operating speed.
Innovation Solution
The implementation of head switches and foot switches in memory arrays, where head switches disconnect memory cells from bit lines during sleep mode to reduce leakage current, and foot switches limit leakage in peripheral circuits by disconnecting them from circuit ground, using high-Vt transistors to minimize impact on performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase integration density and operating speed, then more transistors can be fabricated on an IC die and operating speed improves, but leakage current increases significantly
Solution Approach 1:
The patent extracts and removes the problematic leakage current paths from the memory array by using head switches to disconnect memory cells from bit lines during sleep mode, and foot switches to disconnect peripheral circuits from ground, effectively taking out the harmful leakage current while preserving the compact transistor design
Solution Approach 2:
The patent introduces dynamic control mechanisms (head switches and foot switches) that adaptively connect or disconnect different parts of the memory array based on operational mode (active vs. sleep mode), allowing the system to optimize between high integration density and low leakage current by changing the electrical connectivity state of transistor networks
2Speed
If threshold voltage is reduced to improve operating speed, then transistor switching speed increases, but leakage current increases
Solution Approach 1:
The patent applies different threshold voltage characteristics to different regions of the memory array by using head switches with memory cells and foot switches with peripheral circuits, allowing local optimization where speed-critical paths can use lower Vt transistors while leakage-prone paths use higher Vt transistors or are dynamically disconnected
3Reliability
If power supply voltage is reduced to decrease E-field and prevent oxide breakdown, then transistor reliability improves, but operating speed decreases
Solution Approach 1:
The patent dynamically adjusts the power supply voltage to memory cells and peripheral circuits based on operational mode, using head switches and foot switches to enable full voltage operation during active mode for high speed, and reducing voltage or disconnecting during sleep mode to minimize leakage current, thus adapting between reliability and speed requirements
Data Source
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AI summary
Techniques for reducing leakage current in memory arrays are described. A memory array has multiple rows and multiple columns of memory cells. Bit lines are coupled to the columns of memory cells, and word lines are coupled to the rows of memory cells. The bit lines have disconnected paths to a power supply and float during a sleep mode for the memory array. The bit lines may be coupled to (i) precharge circuits used to precharge the bit lines prior to each read or write operation, (ii) pass transistors used to couple the bit lines to sense amplifiers for read operations, and (iii) pull-up transistors in drivers used to drive the bit lines for write operations. The precharge circuits, pass transistors, and pull-up transistors are turned off during the sleep mode. The word lines are set to a predetermined logic level to disconnect the memory cells from the bit lines during the sleep mode.