Replica Bit Line Circuit for Read-Write Timing and Area Reduction
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Solution Overview
Problem
Conventional semiconductor storage devices require separate circuits for data read and data write operations, leading to increased circuit area overhead.
Innovation Solution
A semiconductor storage device utilizing a replica bit line circuit that generates control signals for both data read and data write operations, integrating a replica bit line circuit with a sense amplifier circuit and a negative potential boost signal generation circuit to optimize timing without additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuits are provided for data read and data write operations, then the reliability of operation signals is improved, but the circuit area increases
Solution Approach 1:
The replica bit line circuit is designed to serve dual purposes: generating startup signals for sense amplifier circuits during data read operations and generating negative potential boost signals during data write operations. This multi-functional design eliminates the need for separate circuits, reducing overall circuit area while maintaining operational reliability.
Solution Approach 2:
The patent merges the functions of the sense amplifier startup signal generation circuit and the negative potential boost signal generation circuit into a single replica bit line circuit. By combining these previously separate circuits, the invention reduces circuit area overhead while ensuring that both read and write operations have reliable signal generation.
2Manufacturing precision
If individual circuits are prepared for data read and data write, then the timing precision of control signals is improved, but the device complexity increases
Solution Approach 1:
The replica bit line circuit performs multiple functions within a unified structure, generating both sense amplifier startup signals and negative potential boost signals with precise timing. This approach maintains timing precision for both read and write operations while avoiding the increased complexity that would result from separate dedicated circuits.
Solution Approach 2:
The replica bit line circuit is segmented into functional portions that can independently generate different control signals at appropriate timing. This segmentation allows the circuit to maintain precise timing for multiple operations while being implemented as a single integrated structure, thereby reducing overall device complexity.
Data Source
AI summary
A semiconductor storage device includes a memory cell array having a plurality of memory cells connected to bit line pairs. At the time of data read from a memory cell, a replica bit line signal is output to a replica bit line in response to a replica word line signal, and a sense amplifier startup signal changes in response to the replica bit line signal whereby a sense amplifier is driven. At the time of data write into a memory cell, a low potential-side bit line of a write-target bit line pair is brought to a negative potential in response to a negative potential boost signal output from a negative potential generation circuit.